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STM8L101xx

8-bit ultralow power microcontroller with up to 8 Kbytes Flash,

multifunction timers, comparators, USART, SPI, I2C

Features

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Main microcontroller features

–Supply voltage range 1.65 V to 3.6 V–Low power consumption (Halt: 0.3µA, Active-halt: 0.8µA, Dynamic Run: 150µA/MHz)

–STM8 Core with up to 16 CISC MIPS throughput

–Temp. range: -40 to 85°C and 125 °C Memories

–Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM–Error correction code (ECC)

–Flexible write and read protection modes–In-application and in-circuit programming–Data EEPROM capability–1.5 Kbytes of static RAM

Clock management

–Internal 16 MHz RC with fast wakeup time (typ. 4µs)

–Internal low consumption 38kHz RC driving both the IWDG and the AWUReset and supply management

–Ultralow power, ultrasafe power-on-reset /power down reset

–Three low power modes: Wait, Active-halt, HaltInterrupt management

–Nested interrupt controller with software priority control

–Up to 29 external interrupt sourcesI/Os

–Up to 30 I/Os, all mappable on external interrupt vectors

–I/Os with prog. input pull-ups, high

sink/source capability and one LED driver infrared output

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UFQFPN32 LQFP32 UFQFPN28 UFQFPN20TSSOP20 ■

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Peripherals

–Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM)

–One 8-bit timer (TIM4) with 7-bit prescaler–Infrared remote control (IR)–Independent watchdog–Auto-wakeup unit

–Beeper timer with 1, 2 or 4 kHz frequencies–SPI synchronous serial interface –Fast I2C Multimaster/slave 400 kHz

–USART with fractional baud rate generator–2 comparators with 4 inputs eachDevelopment support

–Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging–In-circuit emulation (ICE)96-bit unique ID

Device summary

Part number

STM8L101F1, STM8L101F2, STM8L101F3,

STM8L101G2, STM8L101G3STM8L101K3

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Table 1.

Reference

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STM8L101xx

October 2010Doc ID 15275 Rev 111/81

www.st.com

1ContentsSTM8L101xx

Contents

123

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.13.23.33.43.53.63.73.83.93.103.113.123.133.143.153.163.17

Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 10Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4567

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/81 Doc ID 15275 Rev 11

STM8L101xxContents

9Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1.19.1.29.1.39.1.49.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.29.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.3.19.3.29.3.39.3.49.3.59.3.69.3.79.3..3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.4Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.110.2

ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1112

Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

12.112.2

Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 74Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.2.112.2.2

STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.3Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

13Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Doc ID 15275 Rev 113/81

List of tablesSTM8L101xx

List of tables

Table 1.Table 2.Table 3.Table 4.Table 5.Table 6.Table 7.Table 8.Table 9.Table 10.Table 11.Table 12.Table 13.Table 14.Table 15.Table 16.Table 17.Table 18.Table 19.Table 20.Table 21.Table 22.Table 23.Table 24.Table 25.Table 26.Table 27.Table 28.Table 29.Table 30.Table 31.Table 32.Table 33.Table 34.Table 35.Table 36.Table 37.Table 38.Table 39.Table 40.Table 41.Table 42.Table 43.Table 44.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Device features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Legend/abbreviation for table4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Flash and RAM boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Unique ID registers (96 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Total current consumption and timing in Halt and Active-halt mode at

VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Output driving current (PA0 with highsink LED driver capability). . . . . . . . . . . . . . . . . . . . 53NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5x5),

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 69UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4x4),

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70UFQFPN20 3x3mm 0.6 mm mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7120-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4/81 Doc ID 15275 Rev 11

STM8L101xxList of figures

List of figures

Figure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.Figure 10.Figure 11.Figure 12.Figure 13.Figure 14.Figure 15.Figure 16.Figure 17.Figure 18.Figure 19.Figure 20.Figure 21.Figure 22.Figure 23.Figure 24.Figure 25.Figure 26.Figure 27.Figure 28.Figure 29.Figure 30.Figure 31.Figure 32.Figure 33.Figure 34.Figure 35.Figure 36.Figure 37.Figure 38.Figure 39.Figure 40.Figure 41.Figure 42.Figure 43.Figure 44.Figure 45.Figure 46.

STM8L101xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Standard 20-pin UFQFPN package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers. . . . . . . . . . . . . . . . . . . . . . 1520-pin TSSOP package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Standard 28-pin UFQFPN package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728-pin UFQFPN package pinout for STM8L101G3U6ATR and

STM8L101G2U6ATR part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38IDD(RUN) vs. VDD, fCPU=2MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42IDD(RUN) vs. VDD, fCPU= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42IDD(WAIT) vs. VDD, fCPU=2MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43IDD(WAIT) vs. VDD,fCPU= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Typ. IDD(Halt) vs. VDD, fCPU=2 MHz and 16MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Typical HSI accuracy vs. temperature, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Typical HSI accuracy vs. temperature, VDD = 1.65 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . 47Typical LSI RC frequency vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Typical VIL and VIH vs. VDD (standard I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Typical pull-up current IPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Typ. VOL at VDD = 3.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Typ. VOL at VDD = 1.8 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Typ. VOL at VDD = 3.0 V (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Typ. VOL at VDD = 1.8 V (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Typ. VDD - VOH at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Typ. VDD - VOH at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Typical NRST pull-up current Ipu vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Recommended NRST pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5x5). . . . . . 67UFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67LQFP32 - 32-pin low profile quad flat package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . 69LQFP32 recommended footprint(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4x4)(1). . . . 70UFQFPN28 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70UFQFPN20 3x3mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71UFQFPN20 recommended footprint (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 72TSSOP20 recommended footprint (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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List of figuresFigure 47.

STM8L101xx

STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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STM8L101xxIntroduction

1 Introduction

This datasheet provides the STM8L101xx pinout, ordering information, mechanical and

electrical device characteristics.

For complete information on the STM8L101xx microcontroller memory, registers and peripherals, please refer to the STM8L reference manual.

The STM8L101xx devices are members of the STM8L low power 8-bit family. They arereferred to as low-density devices in the STM8L101xx microcontroller family reference manual (RM0013) and in the STM8L Flash programming manual (PM0054).All devices of the SM8L product line provide the following benefits:

●

Reduced system cost–––

Up to 8 Kbytes of low-density embedded Flash program memory including up to 2 Kbytes of data EEPROM

High system integration level with internal clock oscillators and watchdogs.Smaller battery and cheaper power supplies.Up to 16 MIPS at 16 MHz CPU clock frequency

Less than 150µA/MH, 0.8µA in Active-halt mode, and 0.3µA in Halt modeClock gated system and optimized power management

Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.Full documentation and a wide choice of development tools

Advanced core and peripherals made in a state-of-the art technologyProduct family operating from 1.65V to 3.6 V supply

●

Low power consumption and advanced features–––

●

Short development cycles

––

●

Product longevity

––

2 Description

The STM8L101xx low power family features the enhanced STM8 CPU core providing

increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming.All STM8L101xx microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM.

The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different

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DescriptionSTM8L101xx

family very easy, and simplified even more by the use of a common set of development tools.

All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout.

Table 2.Device features

STM8L101xx

2 Kbytes of Flash program

memory

4 Kbytes of Flash program

memory

1.5 Kbytes

Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, Serial peripheral interface (SPI), Inter-integrated circuit (I²C),

Universal synchronous / asynchronous receiver / transmitter (USART),

2 comparators, Infrared (IR) interface

Two 16-bit timers, one 8-bit timer

1.65 to 3.6 V

-40 to +85 °C

UFQFPN28 4x 4UFQFPN20 3x3TSSOP20 4.4 x 6.4

-40 to +85 °C or -40 to +125 °CUFQFPN28 4x4UFQFPN20 3x3UFQFPN32LQFP328 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROM

FeaturesFlashRAM

Peripheral functions

TimersOperating voltageOperating temperature

PackagesUFQFPN20 3x3

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STM8L101xxProduct overview

3 Product overview

Figure 1.

STM8L101xx device block diagram

@VDD16 MHz int RC 38 kHz int RC

Clock

controllerClocksto core andperipherals

VDD18PowerVolt. reg.

VDD =1.65 V to 3.6 VVSSResetPOR/PDR

NRSTSTM8Coreup to 16 MHz

Nested interruptcontrollerup to 29 external

interruptsDebug module

(SWIM)Infrared interface

Port APort BPort CPort D

Address and data busUp to 8 KbytesFlash memory(includingup to 2 Kbytesdata EEPROM)1.5 KbytesSRAMUSARTI²C1multimaster

SPI16-bit Timer 216-bit Timer 38-bit Timer 4

IWDG AWU

RX, TX, CKSWIMSDA, SCLIR_TIMMOSI, MISO, SCK, NSSTIM2_CH[2:1]TIM2_TRIGTIM3_CH[2:1]TIM3_TRIGPA[6:0]PB[7:0]PC[6:0]PD[7:0]COMP1_CH[4:1]COMP1

COMP_REFCOMP2_CH[4:1]COMP2

Beeper

BEEPLegend:

AWU: Auto-wakeup unit

Int. RC: internal RC oscillator

I²C: Inter-integrated circuit multimaster interfacePOR/PDR: Power on reset / power down resetSPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous / asynchronous receiver / transmitterIWDG: Independent watchdog

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Product overviewSTM8L101xx

3.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions.

3.2 Development tools

Development tools for the STM8 microcontrollers include:

●●●

The STice emulation system offering tracing and code profiling

The STVD high-level language debugger including C compiler, assembler and

integrated development environmentThe STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

3.3 Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

3.4 Interrupt controller

The STM8L101xx features a nested vectored interrupt controller:

●●●●

Nested interrupts with 3 software priority levels26 interrupt vectors with hardware priorityUp to 29 external interrupt sources on 10 vectorsTrap and reset interrupts

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STM8L101xxProduct overview

3.5 Memory

The STM8L101xx devices have the following main features:

●●

1.5 Kbytes of RAM

The EEPROM is divided into two memory arrays (see the STM8L reference manual for details on the memory mapping): –

Up to 8Kbytes of low-density embedded Flash program including up to 2Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS). option bytes (one block) of which 5 bytes are already used for the device.

–

Error correction code is implemented on the EEPROM.

3.6 Low power modes

To minimize power consumption, the product features three low power modes:

●●●

Wait mode: CPU clock stopped, selected peripherals at full clock speed.

Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit.

Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. Wakeup is triggered by an external interrupt.

3.7 Voltage regulators

The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power

supply for the core and peripherals.

This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

3.8 Clock control

The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock

to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.

In addition, a 38kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU).

3.9 Independent watchdog

The independent watchdog (IWDG) peripheral can be used to resolve processor

malfunctions due to hardware or software failures.

It is clocked by the 38kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.

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Product overviewSTM8L101xx

3.10 Auto-wakeup counter

The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.

3.11 General purpose and basic timers

STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one

8-bit basic timer (TIM4).

16-bit general purpose timers

The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:

●●●●●

Time base generation

Measuring the pulse lengths of input signals (input capture)

Generating output waveforms (output compare, PWM and One pulse mode)Interrupt capability on various events (capture, compare, overflow, break, trigger)Synchronization with other timers or external signals (external clock, reset, trigger and enable)

8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable

prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Beeper

The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38kHz.

3.13 Infrared (IR) interface

The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.14 Comparators

The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage).

Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted.

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STM8L101xxProduct overview

3.15 USART

The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

3.16 SPI

The serial peripheral interface (SPI) provides half/ full duplex synchronous serial

communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration.

3.17 I²C

The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between

the microcontroller and the serial I2C bus. It provides multi-master capability, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes.

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Pin descriptionSTM8L101xx

4 Pin description

Figure 2.

Standard 20-pin UFQFPN package pinout

PA0 (HS) / SWIM / BEEP / IR_TIMPC4 (HS) / USART_CK / CCOPC2 (HS) / USART_RXPC3 (HS) / USART_TX20191817

NRST / PA1 (HS)

PA2 (HS)PA3 (HS)

VSSVDD

PC1 / I²C_SCL16

1514131211

12345

PC0 / I²C_SDAPB7 (HS) / SPI_MISOPB6 (HS) / SPI_MOSIPB5 (HS) / SPI_SCKPB4 (HS) / SPI_NSS

1.HS corresponds to 20 mA highsink/sourcecapability.

2.Highsink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Note:

The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available on Port A6 in the 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers (Figure3 on page15).

14/81 Doc ID 15275 Rev 11

PB3 (HS) / TIM2_TRIG / COMP2_CH2PB0 (HS) / TIM2_CH1 / COMP1_CH1PB1 (HS) / TIM3_CH1 /COMP1_CH2PD0 (HS) / TIM3_CH2 / COMP1_CH3PB2 (HS) / TIM2_CH2 / COMP2_CH1STM8L101xx

Figure 3.

Pin description

20-pin UFQFPN package pinout for STM8L101F1U6ATR,STM8L101F2U6ATR and STM8L101F3U6ATR part numbers

PA0 (HS) / SWIM / BEEP / IR_TIMPC4 (HS) / USART_CK / CCOPC2 (HS) / USART_RXPC3 (HS) / USART_TX20191817

NRST / PA1 (HS)

PA2 (HS)

PA6 (HS) / COMP_REF

VSSVDD

PC1 / I²C_SCL16

1514131211

12345

PC0 / I²C_SDAPB7 (HS) / SPI_MISOPB6 (HS) / SPI_MOSIPB5 (HS) / SPI_SCKPB4 (HS) / SPI_NSS

1.Please refer to the warning below.

2.HS corresponds to 20 mA highsink/sourcecapability.

3.Highsink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Warning:

For the STM8L101F1U6ATR, STM8L101F2U6ATR and

STM8L101F3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be

considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

Doc ID 15275 Rev 11

PB3 (HS) / TIM2_TRIG / COMP2_CH2PD0 (HS) / TIM3_CH2 / COMP1_CH3PB0 (HS) / TIM2_CH1 / COMP1_CH1PB2 (HS) / TIM2_CH2 / COMP2_CH1PB1 (HS) / TIM3_CH1 /COMP1_CH215/81

Pin description

Figure 4.

20-pin TSSOP package pinout

STM8L101xx

PC3 (HS) / USART_TXPC4 (HS) / USART_CK/ CCOPA0 (HS) / SWIM / BEEP / IR_TIM

NRST / PA1 (HS)

PA2 (HS)PA3 (HS)

VSSVDD

PD0 (HS) / TIM3_CH2 / COMP1_CH3PB0 (HS) / TIM2_CH1 / COMP1_CH1

123456 7 8 9 10

201918171615 14 13 12 11

PC2 (HS) / USART_RXPC1 / I²C_SCLPC0 / I²C_SDAPB7 (HS) / SPI_MISOPB6 (HS) / SPI_MOSIPB5 (HS) / SPI_SCKPB4 (HS) / SPI_NSS

PB3 (HS) /TIM2_TRIG /COMP2_CH2PB2 (HS) / TIM2_CH2 / COMP2_CH1PB1 (HS) / TIM3_CH1 / COMP1_CH2

1.HS corresponds to 20 mA highsink/sourcecapability.

2.Highsink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

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STM8L101xx

Figure 5.

Standard 28-pin UFQFPN package pinout

PA0 (HS) / SWIM / BEEP / IR_TIMPC4 (HS) / USART_CK / CCOPin description

PC2 (HS) / USART_RX23PC3 (HS) / USART_TX2827262524

PC1 / I²C_SCL2221201918171615

PC6 (HS)PC5 (HS)NRST / PA1 (HS)

PA2 (HS)PA3 (HS)

PA4 (HS) / TIM2_BKINPA5 (HS) / TIM3_BKIN

VSSVDD

12345678

PC0 / I²C_SDAPD4 (HS)

PB7 (HS) / SPI_MISOPB6 (HS) / SPI_MOSIPB5 (HS) / SPI_SCKPB4 (HS) / SPI_NSS

PB3 (HS) / TIM2_TRIG / COMP2_CH2

PD1 (HS) / TIM3_TRIG / COMP1_CH4PD2(HS) / COMP2_CH3PD0 (HS) / TIM3_CH2 / COMP1_CH3PD3(HS) / COMP2_CH4PB0 (HS) / TIM2_CH1 / COMP1_CH1PB1 (HS) / TIM3_CH1 / COMP1_CH21.HS corresponds to 20 mA highsink/sourcecapability.

2.Highsink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Note:

The COMP_REF pin is not available in this standard 28-pin UFQFPN package. It is available on Port A6 in the 28-pin UFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (Figure6 on page18).

Doc ID 15275 Rev 11

PB2 (HS) / TIM2_CH2 / COMP2_CH117/81

Pin description

Figure 6.

28-pin UFQFPN package pinout for STM8L101G3U6ATR andSTM8L101G2U6ATR part numbers

PA0 (HS) / SWIM / BEEP / IR_TIMPC4 (HS) / USART_CK / CCOSTM8L101xx

PC2 (HS) / USART_RX23PC3 (HS) / USART_TX2827262524

PC1 / I²C_SCL2221201918171615

PC6 (HS)PC5 (HS)NRST / PA1 (HS)

PA2 (HS)PA3 (HS)

PA4 (HS) / TIM2_BKINPA6 (HS) / COMP_REF

VSSVDD

12345678

PC0 / I²C_SDAPD4 (HS)

PB7 (HS) / SPI_MISOPB6 (HS) / SPI_MOSIPB5 (HS) / SPI_SCKPB4 (HS) / SPI_NSS

PB3 (HS) / TIM2_TRIG / COMP2_CH2

2.Highsink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Warning:

For the STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

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PB2 (HS) / TIM2_CH2 / COMP2_CH1STM8L101xx

Figure 7.

32-pin package pinout

PA0 (HS) / SWIM / BEEP / IR_TIMPin description

PC4 (HS) / USART_CK / CCOPC2 (HS) / USART_RXPC3 (HS) / USART_TX32313029282726252423222120191817PC0 / I²C_SDAPC1 / I²C_SCLPC6 (HS)PC5 (HS)NRST / PA1 (HS)

PA2 (HS)

PA3 (HS)

PA4 (HS) / TIM2_BKINPA5 (HS) / TIM3_BKINPA6 (HS) / COMP_REF

VSS

VDD

123456710111213141516PD7 (HS)PD6 (HS)PD5 (HS)

PD4 (HS)

PB7 (HS)/ SPI_MISOPB6 (HS) / SPI_MOSIPB5 (HS) / SPI_SCKPB4 (HS) / SPI_NSS

PD1 (HS) / TIM3_TRIG / COMP1_CH41.Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package.2.HS corresponds to 20 mA highsink/sourcecapability.

3.Highsink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Doc ID 15275 Rev 11

PB3 (HS) / TIM2_TRIG / COMP2_CH2PB0 (HS) / TIM2_CH1 / COMP1_CH1PB1 (HS) / TIM3_CH1 / COMP1_CH2PD0 (HS) / TIM3_CH2 / COMP1_CH3PB2 (HS) / TIM2_CH2 / COMP2_CH1PD2 (HS) / / COMP2_CH3PD3 (HS) / COMP2_CH419/81

Pin description

Table 3.

TypeLevel

STM8L101xx

Legend/abbreviation for table4

I= input, O = output, S = power supplyInputOutput

CM = CMOS

HS = high sink/source (20 mA)float = floating, wpu = weak pull-up

T = true open drain, OD = open drain, PP = push pull

Port and control InputconfigurationOutputReset state

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state).

Table 4.STM8L101xx pin description

Input

Output

Pin numberUFQFPN20 with COMP_REF(1)UFQFPN28 with COMP_REF(1)UFQFPN32 or LQFP32standard UFQFPN20standard UFQFPN28High sink/sourceExt. interrupt TSSOP20Main function(after reset)ResetPort A2Port A3Port A4Port A5Port A6GroundPort D0Port D1Port D2Port D3

TypefloatingwpuODPin nameAlternate function

123---456

12---3456

456---7

12345-678

1234-5678

1234567

NRST/PA1(2)PA2PA3

PA4/TIM2_BKINPA5/TIM3_BKINPA6/COMP_REFVSSVDD

PD0/TIM3_CH2/COMP1_CH3

I/OI/OXI/OXI/OXI/OXI/OXSSI/OX

XXXXXX

XXXXX

HSHSHSHSHSHS

XXXXXX

PPPA1

Timer 2 - break inputTimer 3 - break inputComparator external reference

Power supply

Timer 3 - channel 2 / Comparator 1 - channel 3Timer 3 - trigger / Comparator 1 - channel 4Comparator 2 -channel 3Comparator 2 -channel 4

---99

PD1/TIM3_TRIG/10

COMP1_CH4

PD2/

COMP2_CH3 PD3/

COMP2_CH4

I/OXXXHSXX

---

101011111112

I/OXI/OX

HSHS

20/81 Doc ID 15275 Rev 11

STM8L101xxTable 4.

STM8L101xx pin description (continued)

Input

Output

Pin description

Pin numberUFQFPN20 with COMP_REF(1)UFQFPN28 with COMP_REF(1)UFQFPN32 or LQFP32standard UFQFPN20standard UFQFPN28wpuODPin name

High sink/sourceExt. interrupt TSSOP20Main function(after reset)Port B0Port B1Port B2Port B3Port B4Port B5Port B6Port B7Port D4Port D5Port D6Port D7Port C0Port C1Port C2Port C3Port C4Port C5

TypefloatingAlternate function

PP77

PB0/TIM2_CH1/

10121213

COMP1_CH1 (3)PB1/TIM3_CH1/

11131314

COMP1_CH2PB2/ TIM2_CH2/

12141415

COMP2_CH1/

I/OX

(3)

XHSXX

Timer 2 - channel 1 / Comparator 1 - channel 1

Timer 3 - channel 1 / Comparator 1 - channel 2

Timer 2 - channel 2 / Comparator 2 - channel 1Timer 2 - trigger / Comparator 2 - channel 2SPI master/slave selectSPI clock

SPI master out/ slave in

SPI master in/ slave out

88I/OXXXHSXX

99I/OXXXHSXX

PB3/TIM2_TRIG/

101013151516

COMP2_CH2111114161617PB4/SPI_NSS(3)121215171718PB5/SPI_SCK131316181819PB6/SPI_MOSI141417191920PB7/SPI_MISO------------202021PD4------22PD523PD624PD7

I/OXXXHSXX

I/OX(3)X(3)XI/OXI/OXI/OXI/OXI/OXI/OXI/OXI/OXI/OXI/OXI/OX

XXXXXXXXXXX

XXXXXXXXXXXXX

HSHSHSHSHSHSHSHS

XXXXXXXXT(4)T(4)

XXXXXXXX

151518212125PC0/I2C_SDA161619222226PC1/I2C_SCL171720232327PC2/USART_RX18181

I2C data I2C clockUSART receiveUSART transmitUSART synchronous clock / Configurable clock output

HSHSHSHS

XXXX

242428PC3/USART_TX

19192---

PC4/USART_CK/

252529I/OX

CCO262630PC5

I/OX

Doc ID 15275 Rev 1121/81

Pin descriptionTable 4.

STM8L101xx pin description (continued)

Input

Output

STM8L101xx

Pin numberUFQFPN20 with COMP_REF(1)UFQFPN28 with COMP_REF(1)UFQFPN32 or LQFP32standard UFQFPN20standard UFQFPN28wpuODPin name

High sink/sourceExt. interrupt TSSOP20Main function(after reset)Port C6Port A0

TypefloatingAlternate function

---272731PC6282832

PA0/SWIM/BEEP/IR_TIM (6)

(5)

I/OXI/OX

XXHSXXX

PP20203

X(5)XHS(6)X

SWIM input and out-put /Beep out-put/Timer Infrared output

1.Please refer to the warning below.

2.At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be

configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L101xx reference manual (RM0013).3.A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.4.In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not

implemented).5.The PA0 pin is in input pull-up during the reset phase and after reset release.6.Highsink LED driver capability available on PA0.

Warning:

For the STM8L101F1U6ATR, STM8L101F2U6ATR, STM8L101F3U6ATR, STM8L101G2U6ATR and

STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be

22/81 Doc ID 15275 Rev 11

STM8L101xxMemory and register map

5 Memory and register map

Figure 8.

Memory map

0x00 0000

RAM

(1.5 Kbytes) (1)

includingStack

(up to 513bytes) (1)

Reserved

0x00 47FF0x00 4800

Option bytes

0x00 48FF0x 0049000x 0049240x 0049250x 0049300x 0049310x00 49FF0x00 50000x00 57FF0x00 5800

0x00 05FF0x00 0600

ReservedUnique IDReserved

(2)

GPIO and peripheral registers

Reserved

0x00 7EFF

0x00 7F000x00 7FFF0x00 80000x00 807F0x00 8080

CPU/SWIM/Debug/ITC

RegistersInterrupt vectorsLow-density Flash program memory (up to 8 Kbytes) (1)

including Data EEPROM(up to 2 Kbytes)

0x00 9FFF

1.Table5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end

address.2.Refer to Table7 for an overview of hardware register mapping, to Table6 for details on I/O port hardware

registers, and to Table8 for information on CPU/SWIM/debug module controller registers.

Doc ID 15275 Rev 1123/81

Memory and register map

Table 5.

STM8L101xx

Flash and RAM boundary addresses

Size1.5 Kbytes2 Kbytes

Start address0x00 00000x00 80000x00 80000x00 8000

End address0x00 05FF0x00 87FF0x00 8FFF0x00 9FFF

Memory area

RAM

Flash program memory4 Kbytes8 Kbytes

Table 6.

Address0x00 50000x00 50010x00 50020x00 50030x00 50040x00 50050x00 50060x00 50070x00 50080x00 50090x00 500A0x00 500B0x00 500C0x00 500D0x00 500E0x00 500F0x00 50100x00 50110x00 50120x00 5013

I/O Port hardware register map

Block

Port A

PA_DDRPA_CR1PA_CR2PB_ODRPB_IDR

Port B

PB_DDRPB_CR1PB_CR2PC_ODRPC_IDR

Port C

PC_DDRPC_CR1PC_CR2PD_ODRPD_IDR

Port D

PD_DDRPD_CR1PD_CR2

Port A data output latch registerPort A input pin value registerPort A data direction registerPort A control register 1Port A control register 2Port B data output latch registerPort B input pin value registerPort B data direction registerPort B control register 1Port B control register 2Port C data output latch registerPort C input pin value registerPort C data direction registerPort C control register 1Port C control register 2Port D data output latch registerPort D input pin value registerPort D data direction registerPort D control register 1Port D control register 2

Reset status 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00

24/81 Doc ID 15275 Rev 11

STM8L101xx

Table 7.

Address0x00 50500x00 50510x00 50520x00 50530x00 50540x00 5055

to0x00 509F0x00 50A00x00 50A10x00 50A20x00 50A30x00 50A40x00 50A50x00 50A60x00 50A70x00 50A8

to 0x00 50AF0x00 50B00x00 50B10x00 50B2

to0x00 50BF0x00 50C00x00 50C1

to 0x00 50C20x00 50C30x00 50C40x00 50C50x00 50C6

to 0x00 50DF

CLK_CCORCLK_CKDIVR

RST

RST_CRRST_SR

WFEITC-EXTI

EXTI_CR1EXTI_CR2EXTI_CR3EXTI_SR1EXTI_SR2EXTI_CONFWFE_CR1WFE_CR2

Flash

Memory and register map

General hardware register map

Block

Flash Program memory unprotection

registerData EEPROM unprotection registerFlash in-application programming status

registerReserved area (75 bytes)

External interrupt control register 1External interrupt control register 2External interrupt control register 3External interrupt status register 1External interrupt status register 2External interrupt port select register

WFE control register 1WFE control register 2

Reserved area (8 bytes)

Reset control registerReset status register

Reserved area (14 bytes)

Clock divider registerReserved area (2 bytes)

CLK

CLK_PCKENR

Peripheral clock gating registerReserved (1 byte)

Configurable clock control registerReserved area (25 bytes)

0x00 0x000x03 0x000x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00Reset status 0x00 0x00 0x00 0x000xX0

Doc ID 15275 Rev 1125/81

Memory and register map

Table 7.

Address0x00 50E00x00 50E10x00 50E20x00 50E3

to0x00 50EF0x00 50F00x00 50F10x00 50F20x00 50F30x00 50F4

to0x00 51FF0x00 52000x00 52010x00 52020x00 52030x00 52040x00 5205

to0x00 520F0x00 52100x00 52110x00 52120x00 52130x00 52140x00 52150x00 52160x00 52170x00 52180x00 52190x00 521A

STM8L101xx

General hardware register map (continued)

Block

IWDG

IWDG_PRIWDG_RLR

Reserved area (13 bytes)

AWU_CSR

AWU

AWU_APRAWU_TBR

BEEP

BEEP_CSR

AWU control/status registerAWU asynchronous prescaler buffer

registerAWU timebase selection registerBEEP control/status register

Reserved area (268 bytes)

SPI_CR1SPI_CR2

SPI

SPI_ICRSPI_SRSPI_DR

SPI control register 1SPI control register 2SPI interrupt control register

SPI status registerSPI data register

Reserved area (11 bytes)

I2C_CR1I2C_CR2I2C_FREQRI2C_OARLI2C_OARH

I2C control register 1I2C control register 2I2C frequency register I2C own address register lowI2C own address register highReserved area (1 byte)

I2C

I2C_DRI2C_SR1I2C_SR2I2C_SR3I2C_ITRI2C_CCRLI2C_CCRHI2C_TRISER

I2C data registerI2C status register 1I2C status register 2I2C status register 3I2C interrupt control registerI2C Clock control register lowI2C Clock control register high

I2C TRISE register

0x000x000x000x000x000x000x000x020x000x000x000x000x000x000x000x000x020x00 0x000x3F 0x000x1FReset status0xXX 0x000xFF

0x00 521B0x00 521C0x00 521D

26/81 Doc ID 15275 Rev 11

STM8L101xx

Table 7.

Address0x00 521E

to0x00 522F0x00 52300x00 52310x00 52320x00 52330x00 52340x00 52350x00 52360x00 52370x00 5238

to0x00 524F

USART

USART_SRUSART_DRUSART_BRR1USART_BRR2USART_CR1USART_CR2USART_CR3USART_CR4

Memory and register map

General hardware register map (continued)

Block

Reset status

Reserved area (18 bytes)

USART status registerUSART data registerUSART baud rate register 1USART baud rate register 2USART control register 1USART control register 2USART control register 3USART control register 4

Reserved area (18 bytes)

0xC00xXX0x000x000x000x000x000x00

Doc ID 15275 Rev 1127/81

Memory and register map

Table 7.

Address0x00 52500x00 52510x00 52520x00 52530x00 52540x00 52550x00 52560x00 52570x00 52580x00 52590x00 525A0x00 525B0x00 525C0x00 525D0x00 525E0x00 525F0x00 52600x00 52610x00 52620x00 52630x00 520x00 52650x00 5266

to0x00 527F

TIM2

STM8L101xx

General hardware register map (continued)

Block

Register labelTIM2_CR1TIM2_CR2TIM2_SMCRTIM2_ETRTIM2_IERTIM2_SR1TIM2_SR2TIM2_EGRTIM2_CCMR1TIM2_CCMR2TIM2_CCER1TIM2_CNTRHTIM2_CNTRLTIM2_PSCRTIM2_ARRHTIM2_ARRLTIM2_CCR1HTIM2_CCR1LTIM2_CCR2HTIM2_CCR2LTIM2_BKRTIM2_OISR

Register nameTIM2 control register 1TIM2 control register 2TIM2 slave mode control register TIM2 external trigger registerTIM2 interrupt enable register

TIM2 status register 1TIM2 status register 2TIM2 event generation register TIM2 capture/compare mode register 1TIM2 capture/compare mode register 2TIM2 capture/compare enable register 1

TIM2 counter highTIM2 counter lowTIM2 prescaler registerTIM2 auto-reload register highTIM2 auto-reload register lowTIM2 capture/compare register 1 highTIM2 capture/compare register 1 lowTIM2 capture/compare register 2 highTIM2 capture/compare register 2 low

TIM2 break registerTIM2 output idle state register

Reserved area (26 bytes)

Reset status0x000x000x000x000x000x000x000x000x000x000x000x000x000x000xFF0xFF0x000x000x000x000x000x00

28/81 Doc ID 15275 Rev 11

STM8L101xx

Table 7.

Address0x00 52800x00 52810x00 52820x00 52830x00 52840x00 52850x00 52860x00 52870x00 52880x00 520x00 528A0x00 528B0x00 528C0x00 528D0x00 528E0x00 528F0x00 52900x00 52910x00 52920x00 52930x00 52940x00 52950x00 5296

to 0x00 52DF0x00 52E00x00 52E10x00 52E20x00 52E30x00 52E40x00 52E50x00 52E6

Memory and register map

General hardware register map (continued)

Block

TIM3

TIM3_CCER1TIM3_CNTRHTIM3_CNTRLTIM3_PSCRTIM3_ARRHTIM3_ARRLTIM3_CCR1HTIM3_CCR1LTIM3_CCR2HTIM3_CCR2LTIM3_BKRTIM3_OISR

Register nameTIM3 control register 1TIM3 control register 2TIM3 slave mode control register TIM3 external trigger registerTIM3 interrupt enable register

TIM3 status register 1TIM3 status register 2TIM3 event generation register TIM3 capture/compare mode register 1TIM3 capture/compare mode register 2TIM3 capture/compare enable register 1

TIM3 counter highTIM3 counter lowTIM3 prescaler registerTIM3 auto-reload register highTIM3 auto-reload register lowTIM3 capture/compare register 1 highTIM3 capture/compare register 1 lowTIM3 capture/compare register 2 highTIM3 capture/compare register 2 low

TIM3 break registerTIM3 output idle state register

Reserved area (74 bytes)

TIM4_CR1TIM4_CR2TIM4_SMCRTIM4_IER

TIM4

TIM4_SR1TIM4_EGRTIM4_CNTRTIM4_PSCRTIM4_ARR

TIM4 control register 1TIM4 control register 2TIM4 Slave mode control registerTIM4 interrupt enable register

TIM4 Status register 1TIM4 event generation register

TIM4 counterTIM4 prescaler register TIM4 auto-reload register low

0x000x000x000x000x000x000x000x000xFFReset status0x000x000x000x000x000x000x000x000x000x000x000x000x000x000xFF0xFF0x000x000x000x000x000x00

0x00 52E70x00 52E8

Doc ID 15275 Rev 1129/81

Memory and register map

Table 7.

Address0x00 52E9

to 0x00 52FE0x00 52FF0x00 53000x00 53010x00 5302

COMPIRTIM

IR_CRCOMP_CRCOMP_CSRCOMP_CCS

STM8L101xx

General hardware register map (continued)

Block

Reset status

Reserved area (23 bytes)

Infra-red control registerComparator control registerComparator status registerComparator channel selection register

0x000x000x000x00

Table 8.

Address0x00 7F000x00 7F010x00 7F020x00 7F030x00 7F040x00 7F050x00 7F060x00 7F070x00 7F080x00 7F090x00 7F0A0x00 7F0B

to 0x00 7F5F0x00 7F60 0x00 7F61 0x00 7F6F0x00 7F700x00 7F710x00 7F720x00 7F730x00 7F74

CPU/SWIM/debug module/interrupt controller registers

Block

APCEPCHPCLXH

CPU

XLYHYLSPHSPLCC

Program counter extended Program counter highProgram counter lowX index register highX index register lowY index register highY index register lowStack pointer highStack pointer lowCondition code register

Reserved area (85 bytes)

CFG

CFG_GCR

Global configuration register

Reserved area (15 bytes)

ITC_SPR1ITC_SPR2ITC_SPR3

ITC-SPR

(1)

Reset status0x000x000x800x000x000x000x000x000x050xFF0x28

0x00

Interrupt Software priority register 1Interrupt Software priority register 2Interrupt Software priority register 3Interrupt Software priority register 4Interrupt Software priority register 5Interrupt Software priority register 6Interrupt Software priority register 7Interrupt Software priority register 8

0xFF0xFF0xFF0xFF0xFF0xFF0xFF0xFF

ITC_SPR4ITC_SPR5ITC_SPR6ITC_SPR7ITC_SPR8

0x00 7F750x00 7F760x00 7F77

30/81 Doc ID 15275 Rev 11

STM8L101xx

Table 8.

Address0x00 7F78

to 0x00 7F790x00 7F800x00 7F81

to0x00 7F8F0x00 7F900x00 7F910x00 7F920x00 7F930x00 7F940x00 7F950x00 7F960x00 7F970x00 7F980x00 7F990x00 7F9A

DM_BK1REDM_BK1RHDM_BK1RLDM_BK2REDM_BK2RHDM_BK2RLDM_CR1DM_CR2DM_CSR1DM_CSR2DM_ENFCTR

SWIM

SWIM_CSR

Memory and register map

CPU/SWIM/debug module/interrupt controller registers (continued)

Block

Reset status

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

Breakpoint 1 register extended byteBreakpoint 1 register high byteBreakpoint 1 register low byteBreakpoint 2 register extended byteBreakpoint 2 register high byteBreakpoint 2 register low byteDebug module control register 1Debug module control register 2Debug module control/status register 1Debug module control/status register 2

Enable function register

0xFF0xFF0xFF0xFF0xFF0xFF0x000x000x100x000xFF0x00

1.Refer to Table7: General hardware register map on page25 (addresses 0x00 50A0 to 0x00 50A5) for a

list of external interrupt registers.

Doc ID 15275 Rev 1131/81

Interrupt vector mappingSTM8L101xx

Table 9.

IRQNo.

Interrupt vector mapping

Interrupt mapping

Description

Wakeup from Halt modeYes-Wakeup Wakeup from from Wait Active-halt (WFI modemode)

Yes-Yes-Wakeup

from Wait (WFE mode)Yes-Yes(1)-Yes(1)-YesYesYesYesYesYesYesYesYesYes

Vectoraddress0x00 80000x00 80040x00 8008

----YesYesYesYesYesYesYesYesYesYes

--Yes-YesYesYesYesYesYesYesYesYesYes

Yes-Yes-YesYesYesYesYesYesYesYesYesYes

0x00 800C0x00 8010-0x00 80170x00 80180x00 801C0x00 80200x00 80240x00 80280x00 802C0x00 80300x00 80340x00 80380x00 803C0x00 80400x00 80440x00 8048

--------Yes

-YesYesYesYesYes-YesYes

-Yes(1)YesYesYes(1)Yes(1)-Yes(1)Yes(1)

0x00 804C-0x00 804F0x00 80500x00 80540x00 80580x00 805C0x00 80600x00 80-0x00 806B0x00 806C0x00 8070

Source blockRESETTRAP

Reset

Software interruptReserved

012-345671011121314151617181920212223-242526

TIM4SPICOMPTIM2TIM2TIM3TIM3EXTIBEXTIDEXTI0EXTI1EXTI2EXTI3EXTI4EXTI5EXTI6EXTI7AWU

FLASH EOP/WR_PG_DISReserved

Auto wakeup from HaltReserved

External interrupt port BExternal interrupt port DExternal interrupt 0External interrupt 1External interrupt 2External interrupt 3External interrupt 4External interrupt 5External interrupt 6External interrupt 7ReservedReservedComparators

Update

/Overflow/Trigger/BreakCapture/CompareUpdate /Overflow/BreakCapture/CompareReservedUpdate /TriggerEnd of Transfer

32/81 Doc ID 15275 Rev 11

STM8L101xxTable 9.

IRQNo.

Interrupt vector mapping

Interrupt mapping (continued)

Description

Wakeup from Halt mode

Wakeup Wakeup from from Wait Active-halt (WFI modemode)

-Yes

Wakeup

from Wait (WFE mode)Yes(1)

Vectoraddress

Source block

27USART

Transmission

complete/transmit data register empty

Receive Register DATA FULL/overrun/idle line detected/parity errorI2C interrupt(2)

-0x00 8074

2829

USARTI2C

-Yes

YesYes

Yes(1)Yes(1)

0x00 80780x00 807C

1.In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes

back to WFE mode. Refer to SectionWait for event (WFE) mode in the RM0013 reference manual.2.The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

Doc ID 15275 Rev 1133/81

Option bytesSTM8L101xx

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated row of the memory.

All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table10 for details on option byte addresses.

Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures.

Table 10.

Addr.

Option bytes

Option nameRead-out protection (ROP)

- UBC (User Boot code size)DATASIZEIndependent watchdog option

Option byte No.OPT1-OPT2OPT3OPT4[1:0]

Option bits

3ROP[7:0]

Must be programmed to 0x00

UBC[7:0]DATASIZE[7:0]

Reserved

IWDG _HALT

IWDG _HW

Factory default setting0x000x000x000x000x00

0x48000x48070x48020x48030x4808

Table 11.

OPT1

Option byte description

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)Refer to Read-out protection section in the STM8L reference manual (RM0013) for details.

UBC[7:0] Size of the user boot code area 0x00: no UBC

0x01-0x02: UBC contains only the interrupt vectors.

0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected...

0x7F - Page 0 to 126 reserved for UBC, memory is write protectedRefer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details.

OPT2

34/81 Doc ID 15275 Rev 11

STM8L101xx

Table 11.

Option byte description (continued)

Option bytes

OPT3

DATASIZE[7:0] Size of the data EEPROM area0x00: no data EEPROM area (1)

0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF(1)0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF(1)... (1)

0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF(1)Refer to Data EEPROM (DATA) section in the STM8L reference manual (RM0013) for more details.

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog reset on Halt/Active-halt0: Independent watchdog continues running in Halt/Active-halt mode1: Independent watchdog stopped in Halt/Active-halt mode

OPT4

1.0x00 is the only allowed value for 4 Kbyte STM8L101xx devices.

Caution:

After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00.

Doc ID 15275 Rev 1135/81

Unique IDSTM8L101xx

8 Unique ID

STM8L101xx devices feature a 96-bit unique device identifier which provides a reference

number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user.

The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.

The unique device identifier is ideally suited:

●●

For use as serial numbers

For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptograhic primitives and protocols before programming the internal memoryTo activate secure boot processes.

Unique ID registers (96 bits)

Content descriptionX co-ordinate on

the waferY co-ordinate on

the waferWafer number

Unique ID bits

3U_ID[7:0]U_ID[15:8]U_ID[23:16]U_ID[31:24]U_ID[39:32]U_ID[47:40]U_ID[55:48]U_ID[63:56]

Lot number

U_ID[71:]U_ID[79:72]U_ID[87:80]U_ID[95:88]

●

Table 12.

Address0x49250x49260x49270x49280x49290x492A0x492B0x492C0x492D0x492E0x492F0x4930

36/81 Doc ID 15275 Rev 11

STM8L101xxElectrical parameters

9 Electrical parameters

9.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

9.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range).

Note:

The values given at 85 °C Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

9.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given

only as design guidelines and are not tested.

9.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

9.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure9.Figure 9.

Pin loading conditions

STM8LPIN

50 pF

Doc ID 15275 Rev 1137/81

Electrical parametersSTM8L101xx

9.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure10.Figure 10.Pin input voltage

STM8LPIN

VIN

9.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.Table 13.

SymbolVDD- VSS

VIN

Voltage characteristics

Ratings

External supply voltage

Input voltage on true open drain pins (PC0 and PC1)(1)

Input voltage on any other pin (2)

Min-0.3VSS-0.3VSS-0.3

Max4.0VDD + 4.04.0

VUnit

VESD

Electrostatic discharge voltage

see Absolute maximum ratings (electrical sensitivity)

on page63

1.Positive injection is not possible on these I/Os. VIN maximum must always be respected. IINJ(PIN) must

STM8L101xx

Table 14.

SymbolIVDDIVSS

Electrical parameters

Current characteristics

Ratings

Total current into VDD power line (source)Total current out of VSS ground line (sink)

Output current sunk by IR_TIM pin (with highsink LED driver capability)

IIO

Output current sunk by any other I/O and control pinOutput current sourced by any I/Os and control pin

IINJ(PIN)

Max.80808025-25-5±5±25

Unit

Injected current on true open-drain pins (PC0 and PC1)(1)Injected current on any other pin (2)

Total injected current (sum of all I/O and control pins) (3)

ΣIINJ(PIN)

1.Positive injection is not possible on these I/Os. VIN maximum must always be respected. IINJ(PIN) must

never be exceeded. A negative injection is induced by VINcannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINpositive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.

Table 15.

SymbolTSTGTJ

Thermal characteristics

Ratings

Storage temperature rangeMaximum junction temperature

Value-65 to +150

150

Unit° C

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Electrical parametersSTM8L101xx

9.3 Operating conditions

Subject to general operating conditions for VDD and TA.

9.3.1

Table 16.

SymbolfMASTER(1)

VDD

General operating conditions

Parameter

Master clock frequency Standard operating voltage

LQFP32UFQFPN32

Power dissipation at TA= 85 °C

for suffix 6 devices

UFQFPN28TSSOP20 Conditions1.65 V ≤ VDD < 3.6 V

Min21.65----------− 40− 40- 40− 40

Max163.62882882501811968318562454985

°C

125105130

°C°CmWUnitMHzV

PD(2)

UFQFPN20LQFP32UFQFPN32

Power dissipation at TA= 125 °C

for suffix 3 devices

UFQFPN28TSSOP20UFQFPN201.65 V ≤ VDD < 3.6 V(6 suffix version)1.65 V ≤ VDD < 3.6 V(3 suffix version)-40 °C ≤ TA ≤ 85 °C(6 suffix version) -40 °C ≤ TA ≤ 125 °C(3 suffix version)

Temperature range

Junction temperature range

1.fMASTER = fCPU

2.To calculate PDmax(TA) use the formula given in thermal characteristics PDmax=(TJmax -TA)/ΘJA with TJmax in this table and

ΘJA in table “Thermal characteristics”

40/81 Doc ID 15275 Rev 11

STM8L101xxElectrical parameters

9.3.2 Power-up / power-down operating conditions

Table 17.

SymboltVDDtTEMPVPOR(1)VPDR(1)

Operating conditions at power-up / power-down

ParameterVDD rise time rate Reset release delayPower on reset threshold

Power down reset threshold

VDD rising

Conditions

Min20-1.351.40

Typ -1--Max1300-1.65(2)1.60

Unitµs/VmsVV

1.Data based on characterization results, not tested in production.2.Data guaranteed, each individual device tested in production.

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Electrical parametersSTM8L101xx

9.3.3 Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

●●

All I/O pins in input mode with a static value at VDD or VSS (no load)All peripherals are disabled except if explicitly mentioned.

Subject to general operating conditions for VDD and TA.Table 18.

Symbol

Total current consumption in Run mode (1)

Parameter

Conditions(2)

fMASTER = 2 MHz

Code executed from

RAM

fMASTER = 4 MHzfMASTER = 8 MHzfMASTER = 16 MHzfMASTER = 2 MHz

Code executed from

Flash

fMASTER = 4 MHzfMASTER = 8 MHzfMASTER = 16 MHz

Typ0.390.550.91.60.550.881.52.7

Max(3)0.60.71.22.1(6)0.71.82.53.5

mAUnit

Supply current in

IDD (Run)

Run

mode(4) (5)

1.Based on characterization results, unless otherwise specified.

2.All peripherals off, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fMASTER3.Maximum values are given for TA = − 40 to 125°C.4.CPU executing typical data processing.

5.An approximate value of IDD(Run) can be given by the following formula:

IDD(Run) = fMASTER x 150 µA/MHz +215 µA.6.Data guaranteed, each individual device tested in production.

Figure 11.IDD(RUN) vs. VDD, fCPU=2MHz10.90.80.7IDD(RUN)HSI [mA]0.60.50.40.30.20.101.61.71.81.922.12.22.32.42.52.62.72.82.933.13.23.33.43.53.6VDD [V]Figure 12.IDD(RUN) vs. VDD, fCPU= 16 MHz 32.92.82.7IDD(RUN)HSI [mA]2.62.52.42.32.22.121.61.71.81.922.12.22.32.42.52.62.72.82.933.13.23.33.43.53.6VDD [V]-40°C25°C85°C125°C-40°C25°C85°C125°Cai17017ai170181.Typical current consumption measured with code executed from Flash.

42/81 Doc ID 15275 Rev 11

STM8L101xxElectrical parameters

Table 19.

Symbol

Total current consumption in Wait mode(1)

Parameter

Conditions

fMASTER = 2 MHz

Typ245300380510

Max(2)400450600800

µAUnit

IDD (Wait)

Supply current in Wait mode CPU not clocked, all peripherals off, HSI internal RC osc.

fMASTER = 4 MHzfMASTER = 8 MHzfMASTER = 16 MHz

1.Based on characterization results, unless otherwise specified.2.Maximum values are given for TA = -40 to 125°C.

Figure 13.IDD(WAIT) vs. VDD, fCPU=2MHz300250Figure 14.IDD(WAIT) vs. VDD,fCPU= 16 MHz600550500IDD(RUN)HSI [µA]15010050025°C85°C125°CIDD(WFI)HSI [µA]200-40°C450400350300250-40°C25°C85°C125°C1.61.71.81.922.12.22.32.42.52.62.72.82.933.13.23.33.43.53.6VDD [V]2001.62.12.6VDD [V]3.13.6ai17015ai170161.Typical current consumption measured with code executed from Flash.

Doc ID 15275 Rev 1143/81

Electrical parameters

Table 20.

Symbol

STM8L101xx

Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V (1)(2)

Parameter

Conditions

TA = -40 °C to 25 °CTA = 55 °C

Supply current in Active-halt LSI RC osc.

TA = 85 °C

mode(at 37 kHz)

TA = 105 °C

TA = 125 °C

Typ0.811.42.95.82

Max Unit22.53.27.513-μAμAμAμAμAmA

IDD(AH)

Supply current during

IDD(WUFAH)wakeup time from Active-halt

modetWU(AH)(3)

Wakeup time from Active-halt mode to Run mode

fCPU= 16 MHzTA = -40 °C to 25 °CTA = 55 °C

IDD(Halt)

Supply current in Halt mode

TA = 85 °CTA = 105 °CTA = 125 °C

IDD(WUFH)tWU(Halt)(3)

Supply current during

wakeup time from Halt mode

Wakeup time from Halt mode

fCPU = 16 MHz

to Run mode

40.350.612.55.424

6.51.2(4)1.82.5(4)6.512(4)-6.5

μsμAμAμAμAμAmAμs

1.TA = -40 to 125 °C, no floating I/O, unless otherwise specified.2.Data based on characterization results, not tested in production.

3.Measured from interrupt event to interrupt vector fetch.

To get tWU for another CPU frequency use tWU(FREQ) = tWU(16 MHz) + 1.5 (TFREQ-T16 MHz). The first word of interrupt routine is fetched 5 CPU cycles after tWU.4.Data guaranteed, each individual device tested in production.

Figure 15.Typ. IDD(Halt) vs. VDD, fCPU=2 MHz and 16MHz76-40°C5I [µA]432101.625°C85°C125°C2.12.6V[V]3.13.6ai17014b1.Typical current consumption measured with code executed from Flash.

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STM8L101xxElectrical parameters

Current consumption of on-chip peripherals

Measurement made for fMASTER = from 2 MHz to 16 MHzTable 21.

SymbolIDD(TIM2)IDD(TIM3)IDD(TIM4)IDD(USART)IDD(SPI)IDD(I²C1)IDD(COMP)

Peripheral current consumption

Parameter

TIM2 supply current (1)TIM3 supply current (1)TIM4 timer supply current (1)USART supply current (2)SPI supply current (2)I2C supply current (2)

Comparator supply current (2)

Typ. VDD = 3.0 V

99474420

µAµA/MHzUnit

1.Data based on a differential IDD measurement between all peripherals off and a timer counter running at

16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in production.2.Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and

not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pin toggling. Not tested in production.

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Electrical parametersSTM8L101xx

9.3.4 Clock and timing characteristics

Internal clock sources

Subject to general operating conditions for VDD and TA.

High speed internal RC oscillator (HSI)

Table 22.

Symbol

HSI oscillator characteristics (1)

Parameter

Conditions

Min--1-2.5-4.5-1.5(2)-2(2)-4.5(2)-70Typ16

Max-1221.5(2)2(2)3(2)100(2)

UnitMHz %%%%%%µA

fHSIFrequency VDD = 3.0 V

VDD = 3.0 V, TA = 25°CVDD = 3.0 V, -10 °C ≤ TA ≤ 85 °C

ACCHSIAccuracy of HSI

oscillator

(factory calibrated)

TA ≤ 125 °CVDD = 3.0 V, -10 °C ≤ TA ≤ 55 °CVDD = 3.0 V, 0 °C ≤

VDD = 3.0 V, -10 °C ≤ TA ≤ 70 °C 3.6 V, 1.65 V ≤ VDD ≤

125 °C-40 °C ≤ TA ≤

IDD(HSI)

HSI oscillator power

consumption

1.VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.2.Data based on characterization results, not tested in production.

Figure 16.Typical HSI frequency vs. VDD1716.816.6HSI frequency [MHz]16.416.21615.815.615.415.2151.651.81.952.12.252.42.552.72.85VDD [V]33.153.33.453.6-40°C25°C85°C125°Cai1701346/81 Doc ID 15275 Rev 11

STM8L101xx

Figure 17.Typical HSI accuracy vs. temperature, VDD = 3 V3.5%3.0%2.5%2.0%1.5%1.0%0.5%0.0% Electrical parameters

3V min3V typical3V max-0.5%-1.0%-1.5%-2.0%-2.5%-3.0%-3.5%-4.0%-4.5%-5.0%-50-40-30-20-100102030405060708090100110120130140ai17021Figure 18.Typical HSI accuracy vs. temperature, VDD = 1.65 V to 3.6 V3.5%3.0%2.5%2.0%1.5%1.0%0.5%0.0% Min 1.65V-3.6VMax 1.65V-3.6V3V typical-0.5%-1.0%-1.5%-2.0%-2.5%-3.0%-3.5%-4.0%-4.5%-5.0%-50-40-30-20-100102030405060708090100110120130140ai17019Low speed internal RC oscillator (LSI)

Table 23.

SymbolfLSIfdrift(LSI)

LSI oscillator characteristics (1)

Parameter

Conditions

Min

Typ38-Max5611

Unit

requency 26LSI oscillator frequency drift(2)

0 °C ≤ TA ≤ 85 °C

-12

kHz %

1.VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.

2.For each individual part, this value is the frequency drift from the initial measured frequency.

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Electrical parameters

Figure 19.Typical LSI RC frequency vs. VDD454341LSI frequency [MHz]39373533312927251.62.1STM8L101xx

-40°C25°C85°C125°C2.6VDD [V]3.13.6ai17012b48/81 Doc ID 15275 Rev 11

STM8L101xxElectrical parameters

9.3.5 Memory characteristics

TA = -40 to 125 °C unless otherwise specified.

Table 24.

SymbolVRM

RAM and hardware registers

ParameterData retention mode (1)

ConditionsHalt mode (or Reset)

Min1.4

Typ-Max-UnitV

1.Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware

registers (only in Halt mode). Guaranteed by characterization, not tested in production.

Flash memory

Table 25.

SymbolVDD

Flash program memory

Parameter

Operating voltage

(all modes, read/write/erase)

Programming time for 1- or -byte (block) erase/write cycles (on programmed byte)Programming time for 1- to -byte (block) write cycles (on erased byte)Programming/ erasing consumptionData retention (program memory) after 10k erase/write cycles at TA = +85 °C

TA=+25 °C, VDD = 3.0 VTA=+25 °C, VDD = 1.8 V

TRET = 55 °C ConditionsfMASTER = 16 MHz

Min 1.65----20(1)

Typ-630.7

Max

(1)

UnitVmsmsmA

3.6-----

tprog

Iprog

tRET

Data retention (data memory) after 10k erase/write cycles at TA = +85 °C

Data retention (data memory) after 300k erase/write cyclesat TA = +125 °C

TRET = 55 °C

20(1)

--years

TRET = 85 °CSee notes (1)(2)See notes

(1)(3)

1(1)10(1)300

(1)(4)

---

NRW

Erase/write cycles (program memory)Erase/write cycles(data memory)

kcycles

1.Data based on characterization results, not tested in production.2.Retention guaranteed after cycling is 10 years at 55 °C.3.Retention guaranteed after cycling is 1 year at 55 °C.

4.Data based on characterization performed on the whole data memory (2 Kbytes).

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Electrical parametersSTM8L101xx

9.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All

unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Table 26.

SymbolVIL

I/O static characteristics (1)

Parameter

Input low level voltage(2)

ConditionsStandard I/OsTrue open drain I/OsStandard I/Os

MinVSS-0.3VSS-0.30.70 x VDD

Typ ---

Max0.3 x VDD0.3 x VDDVDD+0.35.2

UnitV

VIH

Input high level voltage

(2)

True open drain I/OsVDD < 2 V

True open drain I/OsVDD ≥ 2 V

0.70 x VDD

-5.5

Vhys

Schmitt trigger voltage hysteresis (3)

Standard I/OsTrue open drain I/OsVSS≤ VIN≤ VDDStandard I/Os

----

200250--

--50 (5)200(5)200(5)60-

Ilkg

Input leakage current

(4)

VSS≤ VIN≤ VDD

True open drain I/OsVSS≤ VIN≤ VDD

PA0 with high sink LED driver capability

-30-

-455

RPUCIO(7)

Weak pull-up equivalent resistor(6)I/O pin capacitance

VIN=VSS

kΩpF

1.VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.2.Data based on characterization results, not tested in production.

3.Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.4.The max. value may be exceeded if negative current is injected on adjacent pins.5.Not tested in production.

6.RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in

Figure22).7.Data guaranteed by Design, not tested in production.

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STM8L101xx

Figure 20.Typical VIL and VIH vs. VDD (standard I/Os)33Electrical parameters

2.52.5VIL and VIH [V]VIL and VIH [V]22-40°C-40°C25°C25°C85°C85°C125°C125°C1.51.5110.50.5001.61.62.12.12.62.6VDD [V]VDD [V]3.13.13.63.6ai17011Figure 21.Typical VIL and VIH vs. VDD (true open drain I/Os)32.521.510.501.62.12.6VDD [V]3.13.6-40°C25°C85°C125°CVIL and VIH [V]ai17010Figure 22.Typical pull-up resistance RPU vs. VDD with VIN=VSS6055Pull-Up resistance [k]50454035301.651.81.952.12.252.42.552.72.85VDD [V]-40°C25°C85°C125°C33.153.33.453.6ai17009Doc ID 15275 Rev 1151/81

Electrical parameters

Figure 23.Typical pull-up current IPU vs. VDD with VIN=VSS120100STM8L101xx

-40°C25°C85°C125°CPull-Up current [µA]8060402001.651.81.952.12.252.42.552.72.85VDD [V]33.153.33.453.6ai1700852/81 Doc ID 15275 Rev 11

STM8L101xxElectrical parameters

Output driving current

Subject to general operating conditions for VDD and TA unless otherwise specified.Table 27.

Output driving current (standard ports)

Parameter

ConditionsIIO = +2 mA,VDD = 3.0 V

Min---VDD-0.45VDD-0.45VDD-1.2

Max0.450.451.2---UnitVVVVVV

I/O

Symbol

Type

VOL (1)

StandardOutput low level voltage for an I/O pin

IIO = +2 mA,VDD = 1.8 VIIO = +10 mA,VDD = 3.0 VIIO = -2 mA,VDD = 3.0 V

VOH (2)

Output high level voltage for an I/O pin

IIO = -1 mA,VDD = 1.8 VIIO = -10 mA,VDD = 3.0 V

1.The IIO current sunk must always respect the absolute maximum rating specified in Table14 and the sum

of IIO (I/O ports and control pins) must not exceed IVSS.2.The IIO current sourced must always respect the absolute maximum rating specified in Table14 and the

sum of IIO (I/O ports and control pins) must not exceed IVDD.

Table 28.Output driving current (true open drain ports)

Parameter

ConditionsIIO = +3 mA,VDD = 3.0 VIIO = +1 mA,VDD = 1.8 V

Min--Max0.450.45

UnitVV

I/O

Symbol

TypeOpen drainVOL (1)

Output low level voltage for an I/O pin

1.The IIO current sunk must always respect the absolute maximum rating specified in Table14 and the sum

of IIO (I/O ports and control pins) must not exceed IVSS.

Table 29.Output driving current (PA0 with highsink LED driver capability)

Parameter

Output low level voltage for an I/O pin

ConditionsIIO = +20 mA,VDD = 2.0 V

Min-Max0.9

UnitV

I/O

Symbol

Type

VOL (1)

IR1.The IIO current sunk must always respect the absolute maximum rating specified in Table14 and the sum

of IIO (I/O ports and control pins) must not exceed IVSS.

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Electrical parameters

STM8L101xx

Figure 25.Typ. VOL at VDD = 1.8 V (standard

ports)0.5Figure 24.Typ. VOL at VDD = 3.0 V (standard

ports)1.51.251VOL [V]0.750.50.2500510IOL [mA]152025-40°C25°C85°C125°C-40°C25°C85°CVOL [V]0.4125°C0.30.20.100123IOL [mA]4567ai17005

ai17004Figure 26.Typ. VOL at VDD = 3.0 V (true open

drain ports)0.5Figure 27.Typ. VOL at VDD = 1.8 V (true open

drain ports)0.5-40°C0.425°C85°C125°CVOL [V]0.4-40°C25°C85°C125°C0.3VOL [V]0.30.20.20.10.100123IOL [mA]456000.511.5IOL [mA]22.53ai17003

ai17002Figure 28.Typ. VDD - VOH at VDD = 3.0 V

(standard ports)2Figure 29.Typ. VDD - VOH at VDD = 1.8 V

(standard ports)0.4-40°C25°C85°C1.751.5VDD - VOH [V]1.2510.750.50.25002-40°C25°C85°CVDD - VOH [V]0.3125°C125°C0.20.14681012IOH [mA]14161820222400123IOH [mA]456ai17001 54/81 Doc ID 15275 Rev 11STM8L101xxElectrical parameters

NRST pin

The NRST pin input driver is CMOS. A permanent pull-up is present. RPU(NRST) has the same value as RPU (see Table26 on page50).

Subject to general operating conditions for VDD and TA unless otherwise specified.Table 30.

SymbolVIL(NRST)VIH(NRST)VOL(NRST)RPU(NRST)VF(NRST)tOP(NRST)VNF(NRST)

NRST pin characteristicsParameter

NRST input low level voltage (1)NRST input high level voltage (1)NRST output low level voltage NRST pull-up equivalent resistor (2)NRST input filtered pulse (3)NRST output pulse widthNRST input not filtered pulse (3)

IOL = 2 mAConditions

MinVSS1.4-30-20300

Typ (1)

---45---Max0.8VDDVDD-0.86050--kΩnsnsnsVUnit

1.Data based on characterization results, not tested in production.

2.The RPU pull-up equivalent resistor is based on a resistive transistor (Figure30). Corresponding IPU current

characteristics are described in Figure31.3.Data guaranteed by design, not tested in production.

Figure 30.Typical NRST pull-up resistance RPU vs. VDD6055-40°C25°C85°C125°CPull-Up resistance [k]50454035301.651.81.952.12.252.42.552.72.85VDD [V]33.153.33.453.6ai17007Doc ID 15275 Rev 1155/81

Electrical parameters

Figure 31.Typical NRST pull-up current Ipu vs. VDD120100STM8L101xx

-40°C25°C85°C125°CPull-Up current [µA]8060402001.651.81.952.12.252.42.552.72.85VDD [V]33.153.33.453.6ai17006The reset network shown in Figure32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table30. Otherwise the reset is not taken into account internally. For power consumption- sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nFFigure 32.Recommended NRST pin configuration

VDD

RPU

EXTERNALRESETCIRCUIT

0.1μF

RSTINFilter

INTERNAL RESET

STM8L

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STM8L101xxElectrical parameters

9.3.7 Communication interfaces

Serial peripheral interface (SPI)

Unless otherwise specified, the parameters given in Table31 are derived from tests

performed under ambient temperature, fMASTER frequency and VDD supply voltage

conditions summarized in Section9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 31.

SymbolfSCK1/tc(SCK)tr(SCK)tf(SCK)tsu(NSS)(2)th(NSS)(2)tw(SCKH)(2)tw(SCKL)(2)tsu(MI) (2)tsu(SI)(2)th(MI) (2)th(SI)(2)ta(SO)(2)(3)tdis(SO)(2)(4)tv(SO) (2)tv(MO)(2)th(SO)(2)th(MO)(2)

Data output hold time

SPI characteristics

Parameter

SPI clock frequency

Conditions(1)

Master modeSlave mode

Min 00-4 x TMASTER

80105303150-30--151

Max8830--145----3x TMASTER

-6020--nsUnitMHz

SPI clock rise and fall timeCapacitive load: C = 30 pFNSS setup time NSS hold timeSCK high and low timeData input setup time

Slave modeSlave mode

Master mode,

fMASTER = 8 MHz, fSCK= 4 MHzMaster modeSlave modeMaster modeSlave modeSlave modeSlave mode

Slave mode (after enable edge)Master mode

(after enable edge)

Slave mode (after enable edge)Master mode

(after enable edge)

Data input hold timeData output access timeData output disable timeData output valid timeData output valid time

1.Parameters are given by selecting 10-MHz I/O output frequency.

2.Values based on design simulation and/or characterization results, and not tested in production.

3.Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.4.Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

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Electrical parameters

Figure 33.SPI timing diagram - slave mode and CPHA = 0STM8L101xx

NSS inputtSU(NSS)SCK Inputtc(SCK)th(NSS)CPHA=0CPOL=0CPHA=0CPOL=1tw(SCKH)tw(SCKL)tv(SO)MSBOUTtsu(SI)tr(SCK)tf(SCK)LSBOUTta(SO)MISOOUTPUTMOSIINPUTth(SO)BIT6OUTtdis(SO)MSBINth(SI)BIT1INLSBINai14134Figure 34.SPI timing diagram - slave mode and CPHA = 1(1)

NSS inputtSU(NSS)SCK InputCPHA=1CPOL=0CPHA=1CPOL=1tc(SCK)th(NSS)tw(SCKH)tw(SCKL)tv(SO)MSBOUTtsu(SI)th(SI)MSBINBIT1INLSBINtr(SCK)tf(SCK)ta(SO)MISOOUTPUTMOSIINPUTth(SO)BIT6OUTtdis(SO)LSBOUTai141351.Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

58/81 Doc ID 15275 Rev 11

STM8L101xx

Figure 35.SPI timing diagram - master mode(1)

HighNSS inputtc(SCK)SCK InputCPHA=0CPOL=0CPHA=0CPOL=1Electrical parameters

SCK InputCPHA=1CPOL=0CPHA=1CPOL=1tsu(MI)MISOINPUTMOSIOUTUTtw(SCKH)tw(SCKL)MSBINth(MI)MSB OUTtv(MO)BIT1 OUTth(MO)ai14136tr(SCK)tf(SCK)BIT6 INLSB INLSB OUT1.Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Electrical parametersSTM8L101xx

Inter IC control interface (I2C)

Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.The STM8L I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below:Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).Table 32.

Symbol

I2C characteristics

Parameter

Standard mode

I2CMin(2)

Max (2)

----1000300----400

Fast mode I2C(1)

Unit

Min (2)1.3 0.6 100 0 (4)--0.6

Max (2)

---900 (3)300300 -μsμsμspFnsμs

tw(SCLL)tw(SCLH)tsu(SDA)th(SDA)tr(SDA)tr(SCL)tf(SDA)tf(SCL)th(STA)tsu(STA)tsu(STO)tw(STO:STA)

SCL clock low timeSCL clock high timeSDA setup timeSDA data hold timeSDA and SCL rise timeSDA and SCL fall timeSTART condition hold timeRepeated START condition setup time

STOP condition setup timeSTOP to START condition time (bus free)

Capacitive load for each bus line

4.74.02500 (3)--4.04.74.04.7-

0.6 -0.6 1.3---400

1.fSCK must be at least 8 MHz to achieve max fast I2C speed (400 kHz).2.Data based on standard I2C protocol requirement, not tested in production.

3.The maximum hold time of the START condition has only to be met if the interface does not stretch the low

period of SCL signal.4.The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL).

Note:

For speeds around 200 kHz, achieved speed can have ± 5% toleranceFor other speed ranges, achieved speed can have ± 2% tolerance

The above variations depend on the accuracy of the external components used.

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STM8L101xxElectrical parameters

Figure 36.Typical application with I2C bus and timing diagram 1)

VDD4.7kΩI2CBUS4.7kΩVDD100Ω100ΩSDASCLSTM8LREPEATEDSTARTSTARTtsu(STA)SDAtw(STO:STA)STARTtf(SDA)SCLtr(SDA)tsu(SDA)th(SDA)STOPth(STA)tw(SCLH)tw(SCLL)tr(SCL)tf(SCL)tsu(STO)1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD

9.3.8 Comparator characteristics

Table 33.

SymbolVIN(COMP_REF)

VINVoffset(2)tSTARTIDD(COMP)

Comparator characteristics

Parameter

Comparator external referenceComparator input voltage rangeComparator offset errorStartup time (after BIAS_EN)Analog comparator consumptionAnalog comparator consumption

during power-down

Comparator propagation delay

100-mV input step with 5-mV overdrive, input rise time = 1 ns

Conditions

Min (1)-0.1-0.25----Typ------Max(1)VDD-1.25VDD+0.25± 203(1)25(1)60(1)2(1)

UnitVVmVµsµAnA

tpropag(2)

--µs

1.Data guaranteed by design, not tested in production.

2.The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the

comparator and must be avoided:

- Negative injection current on the I/Os close to the comparator inputs- Switching on I/Os close to the comparator inputs

- Negative injection current on not used comparator input.- Switching with a high dV/dt on not used comparator input.

These phenomena are even more critical when a big external serial resistor is added on the inputs.

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Electrical parametersSTM8L101xx

9.3.9 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),

the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

●

ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

●

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).Table 34.

SymbolVFESDVEFTB

EMS data

Parameter

Conditions

Level/Class3B3B4A

Voltage limits to be applied on any I/O pin to

LQFP32, VDD = 3.3 V

induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance

LQFP32, VDD = 3.3 V, fHSILQFP32, VDD = 3.3 V, fHSI/2

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STM8L101xxElectrical parameters

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.Table 35.

Symbol

EMI data (1)

Parameter

Conditions

Monitoredfrequency band0.1 MHz to 30 MHz30 MHz to 130 MHz130 MHz to 1 GHzSAE EMI Level

Max vs.

Unit

16 MHz-3-6-51

-dBμV

SEMI

Peak level

VDD = 3.6 V,TA = +25 °C,LQFP32

conforming to IEC61967-2

1.Not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. Table 36.

SymbolVESD(HBM)VESD(CDM)

ESD absolute maximum ratings

Ratings

Electrostatic discharge voltage(human body model)

Electrostatic discharge voltage(charge device model)

Conditions

Maximum value (1)2000

TA = +25 °C

500

VUnit

1.Data based on characterization results, not tested in production.

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Electrical parametersSTM8L101xx

Static latch-up

●

LU: 2 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Electrical sensitivities

Parameter

Static latch-up class

Class II

Table 37.

SymbolLU

9.4 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table16: General operating conditions on page40.

The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation:TJmax = TAmax + (PDmax x ΘJA)Where:

●●●●●

TAmax is the maximum ambient temperature in °C

ΘJA is the package junction-to-ambient thermal resistance in °C/WPDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)

PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip internal power.

PI/Omax represents the maximum power dissipation on output pinswhere:

PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.

/81 Doc ID 15275 Rev 11

STM8L101xx

Table 38.

Symbol

Electrical parameters

Thermal characteristics(1)

Parameter

Thermal resistance junction-ambientLQFP 32 - 7 x 7 mm

Thermal resistance junction-ambientUFQFPN 32 - 5 x 5 mm

ΘJA

Thermal resistance junction-ambientUFQFPN 28 - 4 x 4 mm

Thermal resistance junction-ambientUFQFPN 20 - 3 x 3 mm - 0.6 mmThermal resistance junction-ambientTSSOP 20

Value602580102110

Unit°C/W°C/W°C/W°C/W°C/W

1.Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

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Package characteristicsSTM8L101xx

10 Package characteristics

10.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

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STM8L101xxPackage characteristics

10.2 Package mechanical data

Figure 37.UFQFPN32 - 32-lead ultra thin fine pitch

quad flat no-lead package outline (5x5)(1)(2)(3)

Seating planeCAdddCFigure 38.UFQFPN32 recommended

footprint(1)(4)

A3A1De981617E2bE 13224LPin # 1 IDR = 0.30D2Bottom viewLA0B8_ME1.Drawing is not to scale.

2.All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.

3.There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.4.Dimensions are in millimeters.

Table 39.

UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5x5),package mechanical data

inches(1)

Max0.60.05

Min0.01970

Typ0.02170.00080.006

0.285.10

0.00710.1929

0.00910.19690.1378

5.103.60

0.19290.1339

0.19690.13780.0197

0.20080.14170.0110 0.2008Max0.02360.0020

Dim.

Min

AA1A3bDD2EE2e

4.903.40

Typ0.550.020.152

0.50.00

0.184.90

0.235.003.505.003.500.500

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Package characteristicsTable 39.

STM8L101xx

UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5x5),package mechanical data (continued)

inches(1)

Max0.50

Min0.0118

Typ0.01570.0031

Number of pins

Max0.0197

Dim.

Min

Lddd

0.30

Typ0.400.08

N32

1.Values in inches are converted from mm and rounded to 4 decimal digits.

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STM8L101xx

Package characteristics

Figure 40.LQFP32 recommended

footprint(1)(2)

Figure 39.LQFP32 - 32-pin low profile quad flat

package outline (7x7)(1)

SeatingplaneCAA224A1cccCDD1D3241716A1LL1Kbc0.25 mmGage plane17162525321E3E1E9832Pin 1identification918e5V_FT1.Drawing is not to scale.2.Dimensions are in millimeters.

Table 40.

Dim.

LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data

Min

Typ

Max1.6

0.051.350.30.098.86.8

975.6

8.86.8

975.60.8

0.45

0.61

0.0°

3.5°0.1

Number of pins7.0°

0.0°

0.75

0.0177

9.27.2

0.34650.2677

1.40.37

0.151.450.450.29.27.2

0.0020.05310.01180.00350.34650.2677

0.35430.27560.22050.35430.27560.22050.03150.02360.03943.5°0.0039

7.0°0.02950.36220.2835

0.05510.0146

Min

inches(1)

Typ

Max0.0630.00590.05710.01770.00790.36220.2835

AA1A2bcDD1D3EE1E3eLL1Kccc

N32

1.Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics

Figure 41.UFQFPN28 - 28-lead ultra thin fine pitch

quad flat no-lead package outline (4x4)(1)

STM8L101xx

Figure 42.UFQFPN28 recommended

footprint(1)(2)

AA3De71415A1dddbeE1L2282221L1 A0B0_ME1.Drawing is not to scale2.Dimensions are in millimeters

Table 41.

UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4x4),package mechanical data

inches(1)

Max0.60.05

Min0.01970

Typ0.02170.00080.0060

0.3

0.0071

0.00980.15750.15750.0197

0.450.5

0.00980.0118

0.01380.01570.0031

Number of pins

0.01770.01970.0118Max0.02360.002

Dim.

Min

AA1A3bDEeL1L2ddd

0.250.30.180.50

Typ0.550.020.1520.25440.50.350.40.08

1.Values in inches are converted from mm and rounded to 4 decimal digits.

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STM8L101xxPackage characteristics

Figure 43.UFQFPN20 3x3mm 0.6 mm package

outline (1)Figure 44.UFQFPN20 recommended

footprint (1)(2)

L1DL4e5bE120151610L211eA3dddL3A1A A0A5_MEBJ󰀒󰀘󰀑󰀖󰀑1.Drawing is not to scale2.Dimensions are in millimeters

Table 42.

Symbol

UFQFPN20 3x3mm 0.6 mm mechanical data

millimeters

Min

Typ3.0003.0000.5500.0200.1520.500

0.5000.300

0.5500.3500.1500.200

0.180

0.2500.050

0.300

0.0071

0.6000.400

0.01970.0118

Max3.1003.1000.6000.050

0.01970Min

inches(1)

Typ0.11810.11810.02170.00080.0060.01970.02170.01380.00590.00790.00980.002

0.01180.02360.01570.02360.002Max

DEAA1A3eL1L2L3L4bddd

2.9002.9000.5000

1.Values in inches are rounded to 4 decimal digits

Doc ID 15275 Rev 1171/81

Package characteristicsSTM8L101xx

Figure 45.TSSOP20 - 20-lead thin shrink small

package outline (1) Figure 46.TSSOP20 recommended

footprint (1)(2)

D2011cE1E110αA1ACPbeA2LL1TSSOP20-M1.Drawing is not to scale2.Dimensions are in millimeters

Table 43.

Dim.

20-lead thin shrink small package, mechanical data

Min

Typ

Max1.2

0.050.80.19

0.151.050.30.1

0.096.46.24.3-0.45

6.56.44.40.650.61

0°

8°

0°

0.26.66..5-0.75

0.00350.2520.24410.16930.16930.1693

0.25590.2520.17320.02560.02360.0394

8°

0.0020.03150.0075

0.0394

Min

Typ

inches(1)

Max0.04720.00590.04130.01180.00390.00790.25980.25980.1772-0.0295

AA1A2bCPcDEE1eLL1a

Number of pins

1.Values in inches are converted from mm and rounded to 4 decimal digits.

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STM8L101xxDevice ordering information

11 Device ordering information

Figure 47.STM8L101xx ordering information scheme

Example:Product classSTM8 microcontrollerFamily typeL = Low powerSub-family type101 = sub-familyPin countK = 32 pinsG = 28 pinsF = 20 pins

Program memory size1 = 2 Kbytes2 = 4 Kbytes3 = 8 KbytesPackageU = UFQFPN T = LQFPP = TSSOPTemperature range3 = -40 °C to 125 °C6 = -40 °C to 85 °C

STM8

101

COMP_REF availability on UFQFPN20 and UFQFPN28A = COMP_REF availableBlank = COMP_REF not available

Shipping

TR = Tape and reelBlank = Tray

1.For a list of available options (e.g. memory size, package) and orderable part numbers or for further

information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you.

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STM8 development toolsSTM8L101xx

12 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

12.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer.The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.

STice key features

●●●●●●●●

Occurrence and time profiling and code coverage (new features)Program and data trace recording up to 128 KB recordsRead/write on the fly of memory during emulationIn-circuit debugging/programming via SWIM protocol8-bit probe analyzer

Power supply follower managing application voltages between 1.62 to 5.5 VModularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements

Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8.

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STM8L101xxSTM8 development tools

12.2 Software tools

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual

Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32Kbytes of code is available.

12.2.1 STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming

software is available for free download at www.st.com/mcu. This package includes:ST Visual Develop – Full-featured integrated development environment from ST, featuring

●●●●●●

Seamless integration of C and ASM toolsetsFull-featured debuggerProject managementSyntax highlighting editorIntegrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface.Available toolchains include:

●●●

Cosmic C compiler for STM8 – One free version that outputs up to 32Kbytes of code is available. For more information, see www.cosmic-software.com.

Raisonance C compiler for STM8 – One free version that outputs up to 32Kbytes of code. For more information, see www.raisonance.com.

STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code.

12.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash

microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

Doc ID 15275 Rev 1175/81

Revision historySTM8L101xx

13 Revision history

Table 44.

Date19-Dec-2008

Document revision history

Revision

Initial release.

Added TSSOP28 package

Modified packages on first pageCOMPx_OUT pins removed

Added Figure6: 28-pin TSSOP package pinout on page17Modified Section9: Electrical parameters on page37.Updated UBC[7:0] description in Section7: Option bytes.Updated low power current consumption on cover page.

Updated Table13: Voltage characteristics, Table20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V, Table26: I/O static characteristics, Table30: NRST pin characteristics, and Section9.3.9: EMC characteristics.

Updated PA1/NRST, PC0 and PC1 in Table4: STM8L101xx pin description.

Added ECC feature.

Changed internal RC frequency to 38kHz.

Updated electrical characteristics in Table16, Table18, Table19, Table20, Table22, Table23, and Table26.

Corrected title on cover page.

Changed VFQFPN32 to WFQFPN32 and updated Table39:

UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5x5), package mechanical data.

Updated Table13, Table26, and Table33.

Replaced WFQFPN20 3x3mm 0.8 mm package by UFQFPN20 3x3mm 0.6 mm package (first page, Table16: General operating conditions on page40, Table38: Thermal characteristics on page65, Section10.2: Package mechanical data on page67)Added one UFQFPN20 version with COMP_REF

Modified Figure40: LQFP32 recommended footprint(1) on page69Added IPROG values in Table25: Flash program memory on page49Updated Table31: SPI characteristics on page57

Added STM8L101F3U6ATR part number in Section4: Pin

description on page14 and in Figure47: STM8L101xx ordering information scheme on page73

Changes

22-Apr-20092

24-Apr-20093

14-May-20094

15-May-20095

76/81 Doc ID 15275 Rev 11

STM8L101xx

Table 44.

Date

Revision history

Document revision history (continued)

Revision

Changes

Removed TSSOP28 package

Modified consumption value on first page

Added BEEP_CSR (address 00 50F3h) in Table7: General hardware register map on page25

TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN

replaced with CLK_PCKENR in Table7: General hardware register map on page25

Added graphs in Section9: Electrical parameters on page37

Added tWU(AH) and tWU(Halt) max values in Table20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page44

Modified Table20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page44

Updated Table22: HSI oscillator characteristics on page46, Table23: LSI oscillator characteristics on page47 and Table24: RAM and hardware registers on page49

Modified Table27: Output driving current (standard ports) on page53

Removed note 1 in Table37: Electrical sensitivities on pageAdded note to Table39: UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5x5), package mechanical data on page67 and

Table41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4x4), package mechanical data on page70

12-Jun-20096

Doc ID 15275 Rev 1177/81

Revision history

Table 44.

Date

STM8L101xx

Document revision history (continued)

Revision

Changes

Added STM8L101F2U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers

Modified Section2: Description on page7.

Modified Table2: Device features on page8 (Flash)

Modified Figure1: STM8L101xx device block diagram on page9Modified Section3.5: Memory on page11

Added note below Figure2: Standard 20-pin UFQFPN package pinout on page14 and Figure5: Standard 28-pin UFQFPN package pinout on page17

Added Figure6: 28-pin UFQFPN package pinout for

STM8L101G3U6ATR and STM8L101G2U6ATR part numbers on page18

Modified reset values for Px_IDR registers in Table6: I/O Port hardware register map on page24

Added Section6: Interrupt vector mapping on page32

Modified OPT numbers in Section7: Option bytes on page34Modified OPT2 in Table10: Option bytes on page34Added Section8: Unique ID on page36TIM_IR pin replaced with IR_TIM pin

Modified Table20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page44

Modified Figure15: Typ. IDD(Halt) vs. VDD, fCPU=2 MHz and 16MHz on page44 and Figure19: Typical LSI RC frequency vs. VDD on page48

Modified Table27: Output driving current (standard ports) on page53

Updated Table29: Output driving current (PA0 with highsink LED driver capability) on page53

Modified : Functional EMS (electromagnetic susceptibility) on page62

Modified conditions in Table35: EMI data on page63

Added note to Figure37: UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5x5) on page67

Modified Figure41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4x4)(1) on page70

Added Figure44: UFQFPN20 recommended footprint (1) on page71

Added Figure46: TSSOP20 recommended footprint (1) on page72CMP replaced with COMP

07-Sep-20097

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Table 44.

Date

Revision history

Document revision history (continued)

Revision

Changes

Modified status of the document (datasheet instead of preliminary data)

Replaced WFQFPN32 with UFQFPN32 and WFQFPN28 with UFQFPN28.

Modified title of the reference manual mentioned in Section2: Description on page7

Added references to “low-density” in Section2: Description on page7, Section3.5: Memory on page11 and in Figure8: Memory map on page23

Modified Figure8: Memory map on page23 (unique ID are added)Table7: General hardware register map on page25: Modified reserved areas and IR block replaced with IRTIM block

Modified tTEMP in Table17: Operating conditions at power-up / power-down on page41

Modified Table23: LSI oscillator characteristics on page47Modified Table25: Flash program memory on page49 (tPROG)Modified Table16: General operating conditions on page40 and Table38: Thermal characteristics on page65

Modified Section10: Package characteristics on page66

Modified Introduction and Description

Modified one reserved area (0x00 5055 to 0x00 509F) in Table7: General hardware register map on page25

ModifiedTable4: STM8L101xx pin description on page20: modified note 2 and removed “wpu” for PC0 and PC1

Removed one note to Table22: HSI oscillator characteristics on page46

Modified first paragraph in Section: NRST pin on page55

Modified OPT3 description in Table11: Option byte description on page34

Added note 5 to Table18: Total current consumption in Run mode on page42

Modified VESD(CDM) in Table36: ESD absolute maximum ratings on page63

Modified Figure36: Typical application with I2C bus and timing diagram 1) on page61

Modified COMP_REF availability information in Figure47: STM8L101xx ordering information scheme on page73Modified Section12.2: Software tools on page75

29-Nov-20098

18-Jun-20109

Doc ID 15275 Rev 1179/81

Revision history

Table 44.

Date

STM8L101xx

Document revision history (continued)

Revision

Changes

Modified Table3: Legend/abbreviation for table4 on page20 and Table4: STM8L101xx pin description on page20 (for PA0, PA1, PB0 and PB4)

Modified Table13: Voltage characteristics on page38 and Table14: Current characteristics on page39

Modified VIH in Table26: I/O static characteristics on page50Added notes below UFQFPN32 package

Added STM8L101F1 devices:

Modified Table1: Device summary on page1, Table2: Device features on page8 and Table5: Flash and RAM boundary addresses on page24

Modified warning below Figure3 on page15 and belowTable4: STM8L101xx pin description on page20

Modified Figure47: STM8L101xx ordering information scheme on page73

Modifed text above Figure32: Recommended NRST pin configuration on page56

Modified Figure32 on page56

21-Jul-201010

14-Oct-201011

80/81 Doc ID 15275 Rev 11

STM8L101xx

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