专利内容由知识产权出版社提供
专利名称：Method of forming polysilicon gate
structures with specific edge profiles foroptimization of LDD offset spacing
发明人：Cheng-Ku Chen,Min-Hwa Chi申请号：US10798178申请日：20040311公开号：US07129140B2公开日：20061031
专利附图：
摘要：Methods of forming MOSFET devices featuring LDD regions offset from theedges of conductive gate structures has been developed. A first embodiment of this
invention features the definition of a tapered conductive gate structure with the foot ofthe tapered structure larger in width than the top of the structure. Formation of an LDDregion is accomplished in regions of the semiconductor substrate not covered by thetapered conductive structure. A dry etch procedure is next used to remove the foot ofthe tapered conductive structure resulting in an LDD region being offset from the edgesof a now straight walled conductive structure. A second embodiment of this inventionentails the definition of a conductive gate structure featuring notches located at thebottom of the conductive gate structure, extending inwards. Formation of an LDD regionis again accomplished in regions of the semiconductor substrate not underlying the non-notched portion of the conductive gate structure, resulting in the LDD region beingoffset from the notched edges of the conductive gate structure.
申请人：Cheng-Ku Chen,Min-Hwa Chi
地址：Hsinchu TW,Palo Alto CA US
国籍：TW,US
代理机构：Haynes and Boone, LLP
更多信息请下载全文后查看
