library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
entity shzizhong is
port(
clk,stop,reset,tiaoshi,tiaofen:in std_logic;--停止，复位，调时，调分 功能
miaoling,miaoge,miaoshi:out std_logic_vector(3 downto 0);--对应各自数码管译码器的四 fenge,fenshi,shige,shishi:out std_logic_vector(3 downto 0)); --位二进制输出
end shzizhong;
architecture dong of shzizhong is
signal fen1,fen2,miao1,miao2,shi1,shi2:integer range 0 to 9;
signal miao0_clk,fen1_clk,shi1_clk,miao1_clk:std_logic;
signal jiaoshi_clk,fen_clk,shi_clk:std_logic;
begin
process(CLK,stop) --50M分频为10hz
variable n1:integer range 0 to 2499999;
begin
if rising_edge(Clk) then
if n1<2499999 then n1:=n1+1;
else n1:=0; miao0_clk<=not miao0_clk;
end if;
end if;
end process;
process(miao0_clk)--产生校时信号
variable cq0:std_logic_vector(2 downto 0);
begin
if rising_edge(miao0_Clk) then
if cq0<2 then cq0:=cq0+1;jiaoshi_clk<='0';
else cq0:= (others =>'0');jiaoshi_clk<='1';
end if;
end if;
end process;
process(miao0_clk,reset,stop) --0.1s 10进制计数器
variable cq1:std_logic_vector(3 downto 0);
begin
if stop='0' then
if reset='1' then cq1:= (others =>'0');
elsif rising_edge(miao0_Clk) then
if cq1<9 then cq1:=cq1+1;miao1_clk<='0';
else cq1:= (others =>'0');miao1_clk<='1';
end if;
end if;
end if;
miaoling<=cq1;
end process;
process(miao1_clk,reset,tiaofen,fen1_clk,jiaoshi_clk)-- 秒，variable cq4:integer range 0 to 59;
begin
if reset='1' then cq4:=0;
elsif rising_edge(miao1_Clk) then
if cq4<59 then cq4:=cq4+1;fen1_clk<='0';
else cq4:=0;fen1_clk<='1';
60进制计数器
end if;
end if;
miao2<=cq4 / 10; --对10取整，即调取 十位上的数
miao1 <=cq4 rem 10;-- 对10取余，即调取 个位上的数
fen_clk<= (tiaofen and jiaoshi_clk) or ((not tiaofen) and fen1_clk);--调分的语句
case miao2 is
when 0 => miaoshi<=\"0000\";
when 1 => miaoshi<=\"0001\";
when 2 => miaoshi<=\"0010\";
when 3 => miaoshi<=\"0011\";
when 4 => miaoshi<=\"0100\";
when 5 => miaoshi<=\"0101\";
when others => null;
end case;
case miao1 is
when 0 => miaoge<=\"0000\";
when 1 => miaoge<=\"0001\";
when 2 => miaoge<=\"0010\";
when 3 => miaoge<=\"0011\";
when 4 => miaoge<=\"0100\";
when 5 => miaoge<=\"0101\";
when 6 => miaoge<=\"0110\";
when 7 => miaoge<=\"0111\";
when 8 => miaoge<=\"1000\";
when 9 => miaoge<=\"1001\";
when others => null;
end case;
end process;
process(fen_clk,reset,tiaoshi,jiaoshi_clk,shi1_clk)--分钟，60进制计数器
variable cq5:integer range 0 to 59;
begin
if reset='1' then cq5:=0;
elsif rising_edge(fen_Clk) then
if cq5<59 then cq5:=cq5+1;shi1_clk<='0';
else cq5:=0;shi1_clk<='1';
end if;
end if;
fen2<= cq5 / 10;--对10取整，即调取 十位上的数
fen1 <= cq5 rem 10; --对10取余，即调取 个位上的数
shi_clk<= (tiaoshi and jiaoshi_clk) or ((not tiaoshi) and shi1_clk); --调时的语句
case fen2 is
when 0 => fenshi<=\"0000\";
when 1 => fenshi<=\"0001\";
when 2 => fenshi<=\"0010\";
when 3 => fenshi<=\"0011\";
when 4 => fenshi<=\"0100\";
when 5 => fenshi<=\"0101\";
when others => null;
end case;
case fen1 is
when 0 => fenge<=\"0000\";
when 1 => fenge<=\"0001\";
when 2 => fenge<=\"0010\";
when 3 => fenge<=\"0011\";
when 4 => fenge<=\"0100\";
when 5 => fenge<=\"0101\";
when 6 => fenge<=\"0110\";
when 7 => fenge<=\"0111\";
when 8 => fenge<=\"1000\";
when 9 => fenge<=\"1001\";
when others => null;
end case;
end process;
process(shi_clk,reset)--小时，十二进制计数器
variable cq6:integer range 0 to 11;
begin
if reset='1' then cq6:=0;
elsif rising_edge(shi_Clk) then
if cq6<11 then cq6:=cq6+1;
else cq6:=0;
end if;
end if;
shi1<= cq6 rem 10;
shi2<= cq6 / 10;
case shi2 is
when 0 => shishi<=\"0000\";
when 1 => shishi<=\"0001\";
when others => null;
end case;
case shi1 is
when 0 => shige<=\"0000\";
when 1 => shige<=\"0001\";
when 2 => shige<=\"0010\";
when 3 => shige<=\"0011\";
when 4 => shige<=\"0100\";
when 5 => shige<=\"0101\";
when 6 => shige<=\"0110\";
when 7 => shige<=\"0111\";
when 8 => shige<=\"1000\";
when 9 => shige<=\"1001\";
when others => null;
end case;
end process;
end dong;
--本次EDA实习较简单，是用FPGA芯片 Cyclone:EP1C3T144C8 来设计完成，采用50MHZ的输入时钟，对其进行分频到10HZ 作为最低位的计数时钟，最低位即0.1s的显示，用10进制计数器计 10HZ时钟上升沿的跳变次数，来实现这一位的计时，当出现进位时，10进制计数器清零并输出进位信号（即1s的时钟信号），再用60进制对一秒的信号进行计数，并进位输出一分钟的时钟信号。。。。。直至小时。
