CY7C67200
EZ-OTG™
Programmable USB On-The-GoHost/Peripheral Controller
CypressSemiconductorCorporationDocument #: 38-08014 Rev. *E
•3901NorthFirstStreet•
SanJose, CA 95134•408-943-2600
Revised September 16, 2003
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CY7C67200
TABLE OF CONTENTS
1.0 INTRODUCTION ..............................................................................................................................9
1.1 EZ-OTG Features .......................................................................................................................92.0 TYPICAL APPLICATIONS .............................................................................................................103.0 FUNCTIONAL OVERVIEW ............................................................................................................10
3.1 Processor Core .........................................................................................................................10
3.1.1 Processor ........................................................................................................................................103.1.2 Clocking ..........................................................................................................................................103.1.3 Memory ...........................................................................................................................................103.1.4 Interrupts .........................................................................................................................................103.1.5 General Timers and Watchdog Timer .............................................................................................103.1.6 Power Management ........................................................................................................................10
4.0 INTERFACE DESCRIPTIONS .......................................................................................................11
4.1 USB Interface ............................................................................................................................11
4.1.1 USB Features ..................................................................................................................................124.1.2 USB Pins. ........................................................................................................................................12
4.2 OTG Interface ...........................................................................................................................12
4.2.1 OTG Features .................................................................................................................................124.2.2 OTG Pins. .......................................................................................................................................13
4.3 General Purpose I/O Interface ..................................................................................................13
4.3.1 GPIO Description ............................................................................................................................134.3.2 Unused Pin Descriptions .................................................................................................................13
4.4 UART Interface .........................................................................................................................13
4.4.1 UART Features ...............................................................................................................................134.4.2 UART Pins. .....................................................................................................................................13
4.5 I2C EEPROM Interface .............................................................................................................13
4.5.1 I2C EEPROM Features ...................................................................................................................134.5.2 I2C EEPROM Pins. .........................................................................................................................14
4.6 Serial Peripheral Interface ........................................................................................................14
4.6.1 SPI Features ...................................................................................................................................144.6.2 SPI Pins ..........................................................................................................................................14
4.7 High-Speed Serial Interface ......................................................................................................14
4.7.1 HSS Features ..................................................................................................................................144.7.2 HSS Pins .........................................................................................................................................15
4.8 Host Port Interface (HPI) ...........................................................................................................15
4.8.1 HPI Features ...................................................................................................................................154.8.2 HPI Pins ..........................................................................................................................................15
4.9 Charge Pump Interface .............................................................................................................16
4.9.1 Charge Pump Features ...................................................................................................................1.9.2 Charge Pump Pins ..........................................................................................................................17
4.10 Booster Interface .....................................................................................................................17
4.10.1 Booster Pins. .................................................................................................................................18
4.11 Crystal Interface ......................................................................................................................18
4.11.1 Crystal Pins. ..................................................................................................................................18
4.12 Boot Configuration Interface ...................................................................................................184.13 Operational Modes ..................................................................................................................19
4.13.1 Coprocessor Mode ........................................................................................................................194.13.2 Stand-alone Mode .........................................................................................................................19
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TABLE OF CONTENTS (continued)
5.0 POWER SAVINGS AND RESET DESCRIPTION ..........................................................................20
5.1 Power Savings Mode Description .............................................................................................205.2 Sleep .........................................................................................................................................205.3 External (Remote) wakeup Source ...........................................................................................205.4 Power-On Reset (POR) Description .........................................................................................215.5 Reset Pin ..................................................................................................................................215.6 USB Reset ................................................................................................................................216.0 MEMORY MAP ...............................................................................................................................21
6.1 Mapping ....................................................................................................................................216.2 Internal Memory ........................................................................................................................217.0 REGISTERS ...................................................................................................................................23
7.1 Processor Control Registers .....................................................................................................23
7.1.1 CPU Flags Register [0xC000] [R] .................................................................................................237.1.2 Bank Register [0xC002] [R/W] ......................................................................................................247.1.3 Hardware Revision Register [0xC004] [R] ....................................................................................257.1.4 CPU Speed Register [0xC008] [R/W] ...........................................................................................257.1.5 Power Control Register [0xC00A] [R/W] .......................................................................................267.1.6 Interrupt Enable Register [0xC00E] [R/W] ....................................................................................287.1.7 Breakpoint Register [0xC014] [R/W] .............................................................................................297.1.8 USB Diagnostic Register [0xC03C] [R/W] .....................................................................................30
7.2 Timer Registers .........................................................................................................................31
7.2.1 Watchdog Timer Register [0xC00C] [R/W] ...................................................................................317.2.2 Timer n Register [R/W] ....................................................................................................................32
7.3 General USB Registers .............................................................................................................32
7.3.1 USB n Control Register [R/W] .........................................................................................................32
7.4 USB Host Only Registers ..........................................................................................................34
7.4.1 Host n Control Register [R/W] .........................................................................................................357.4.2 Host n Address Register [R/W] .......................................................................................................357.4.3 Host n Count Register [R/W] ...........................................................................................................367.4.4 Host n Endpoint Status Register [R] ...............................................................................................367.4.5 Host n PID Register [W] ..................................................................................................................387.4.6 Host n Count Result Register [R] ....................................................................................................397.4.7 Host n Device Address Register [W] ...............................................................................................397.4.8 Host n Interrupt Enable Register [R/W] ...........................................................................................407.4.9 Host n Status Register [R/W] ..........................................................................................................417.4.10 Host n SOF/EOP Count Register [R/W] ........................................................................................427.4.11 Host n SOF/EOP Counter Register [R] .........................................................................................427.4.12 Host n Frame Register [R] ............................................................................................................43
7.5 USB Device Only Registers ......................................................................................................43
7.5.1 Device n Endpoint n Control Register [R/W] ...................................................................................447.5.2 Device n Endpoint n Address Register [R/W] .................................................................................457.5.3 Device n Endpoint n Count Register [R/W] .....................................................................................467.5.4 Device n Endpoint n Status Register [R/W] ....................................................................................467.5.5 Device n Endpoint n Count Result Register [R/W] ..........................................................................487.5.6 Device n Interrupt Enable Register [R/W] .......................................................................................497.5.7 Device n Address Register [W] .......................................................................................................517.5.8 Device n Status Register [R/W] .......................................................................................................527.5.9 Device n Frame Number Register [R] .............................................................................................547.5.10 Device n SOF/EOP Count Register [W] ........................................................................................54
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CY7C67200
TABLE OF CONTENTS (continued)
7.6 OTG Control Registers .............................................................................................................55
7.6.1 OTG Control Register [0xC098] [R/W] ..........................................................................................55
7.7 GPIO Registers .........................................................................................................................56
7.7.1 GPIO Control Register [0xC006] [R/W] .........................................................................................577.7.2 GPIO 0 Output Data Register [0xC01E] [R/W] ................................................................................587.7.3 GPIO 1 Output Data Register [0xC024] [R/W] ................................................................................597.7.4 GPIO 0 Input Data Register [0xC020] [R] .....................................................................................597.7.5 GPIO 1 Input Data Register [0xC026] [R] .......................................................................................597.7.6 GPIO 0 Direction Register [0xC022] [R/W] ...................................................................................607.7.7 GPIO 1 Direction Register [0xC028] [R/W] ...................................................................................60
7.8 HSS Registers ..........................................................................................................................61
7.8.1 HSS Control Register [0xC070] [R/W] ..........................................................................................617.8.2 HSS Baud Rate Register [0xC072] [R/W] .....................................................................................637.8.3 HSS Transmit Gap Register [0xC074] [R/W] ..................................................................................637.8.4 HSS Data Register [0xC076] [R/W] ..............................................................................................7.8.5 HSS Receive Address Register [0xC078] [R/W] .............................................................................7.8.6 HSS Receive Counter Register [0xC07A] [R/W] ...........................................................................657.8.7 HSS Transmit Address Register [0xC07C] [R/W] .........................................................................657.8.8 HSS Transmit Counter Register [0xC07E] [R/W] ..........................................................................66
7.9 HPI Registers ............................................................................................................................66
7.9.1 HPI Breakpoint Register [0x0140] [R] .............................................................................................667.9.2 Interrupt Routing Register [0x0142] [R] ...........................................................................................677.9.3 SIEXmsg Register [W] ....................................................................................................................687.9.4 HPI Mailbox Register [0xC0C6] [R/W] ..........................................................................................697.9.5 HPI Status Port [] [HPI: R] ...............................................................................................................70
7.10 SPI Registers ..........................................................................................................................72
7.10.1 SPI Configuration Register [0xC0C8] [R/W] ................................................................................727.10.2 SPI Control Register [0xC0CA] [R/W] .........................................................................................747.10.3 SPI Interrupt Enable Register [0xC0CC] [R/W] ...........................................................................757.10.4 SPI Status Register [0xC0CE] [R] ...............................................................................................767.10.5 SPI Interrupt Clear Register [0xC0D0] [W] ....................................................................................777.10.6 SPI CRC Control Register [0xC0D2] [R/W] .................................................................................777.10.7 SPI CRC Value Register [0xC0D4] [R/W] ...................................................................................787.10.8 SPI Data Register [0xC0D6] [R/W] .............................................................................................797.10.9 SPI Transmit Address Register [0xC0D8] [R/W] .........................................................................797.10.10 SPI Transmit Count Register [0xC0DA] [R/W] ............................................................................797.10.11 SPI Receive Address Register [0xC0DC [R/W] ........................................................................807.10.12 SPI Receive Count Register [0xC0DE] [R/W] ...........................................................................80
7.11 UART Registers ......................................................................................................................81
7.11.1 UART Control Register [0xC0E0] [R/W] ......................................................................................817.11.2 UART Status Register [0xC0E2] [R] ...........................................................................................827.11.3 UART Data Register [0xC0E4] [R/W] ..........................................................................................82
8.0 PIN DIAGRAM ................................................................................................................................839.0 PIN DESCRIPTIONS ......................................................................................................................8410.0 ABSOLUTE MAXIMUM RATINGS ..............................................................................................8511.0 OPERATING CONDITIONS .........................................................................................................8512.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) ...................................................................8613.0 DC CHARACTERISTICS ...........................................................................................................86
13.1 USB Transceiver .....................................................................................................................87
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TABLE OF CONTENTS (continued)
14.0 AC TIMING CHARACTERISTICS ................................................................................................87
14.1 Reset Timing ...........................................................................................................................8714.2 Clock Timing ...........................................................................................................................8814.3 I2C EEPROM Timing ..............................................................................................................8814.4 HPI (Host Port Interface) Write Cycle Timing .........................................................................14.5 HPI (Host Port Interface) Read Cycle Timing .........................................................................9014.6 HSS BYTE Mode Transmit .....................................................................................................9114.7 HSS Block Mode Transmit ......................................................................................................9114.8 HSS BYTE and BLOCK Mode Receive ..................................................................................9114.9 Hardware CTS/RTS Handshake .............................................................................................9215.0 REGISTER SUMMARY ................................................................................................................9316.0 ORDERING INFORMATION ........................................................................................................9717.0 PACKAGE DIAGRAMS ...............................................................................................................97
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CY7C67200
LIST OF FIGURES
Figure 1-1. Block Diagram.......................................................................................................................9Figure 4-1. Charge Pump......................................................................................................................16Figure 4-2. Power Supply Connection With Booster.............................................................................17Figure 4-3. Power Supply Connection Without Booster........................................................................17Figure 4-4. Crystal Interface..................................................................................................................18Figure 4-5. Minimum Standalone Hardware Configuration – Peripheral Only.......................................20Figure 6-1. Memory Map.......................................................................................................................22Figure 7-1. Processor Control Registers...............................................................................................23Figure 7-2. CPU Flags Register.............................................................................................................23Figure 7-3. Bank Register......................................................................................................................24Figure 7-4. Revision Register................................................................................................................25Figure 7-5. CPU Speed Register...........................................................................................................25Figure 7-6. Power Control Register.......................................................................................................26Figure 7-7. Interrupt Enable Register....................................................................................................28Figure 7-8. Breakpoint Register.............................................................................................................29Figure 7-9. USB Diagnostic Register.....................................................................................................30Figure 7-10. Timer Registers.................................................................................................................31Figure 7-11. Watchdog Timer Register..................................................................................................31Figure 7-12. Timer n Register................................................................................................................32Figure 7-13. USB Registers...................................................................................................................32Figure 7-14. USB n Control Register.....................................................................................................33Figure 7-15. USB Host Only Register....................................................................................................34Figure 7-16. Host n Control Register.....................................................................................................35Figure 7-17. Host n Address Register...................................................................................................36Figure 7-18. Host n Count Register.......................................................................................................36Figure 7-19. Host n Endpoint Status Register.......................................................................................37Figure 7-20. Host n PID Register...........................................................................................................38Figure 7-21. Host n Count Result Register............................................................................................39Figure 7-22. Host n Device Address Register.......................................................................................39Figure 7-23. Host n Interrupt Enable Register.......................................................................................40Figure 7-24. Host n Status Register......................................................................................................41Figure 7-25. Host n SOF/EOP Count Register......................................................................................42Figure 7-26. Host n SOF/EOP Counter Register...................................................................................43Figure 7-27. Host n Frame Register......................................................................................................43Figure 7-28. USB Device Only Registers..............................................................................................43Figure 7-29. Device n Endpoint n Control Register...............................................................................44Figure 7-30. Device n Endpoint n Address Register..............................................................................45Figure 7-31. Device n Endpoint n Count Register.................................................................................46Figure 7-32. Device n Endpoint n Status Register.................................................................................47Figure 7-33. Device n Endpoint n Count Result Register......................................................................49Figure 7-34. Device n Interrupt Enable Register...................................................................................49Figure 7-35. Device n Address Register................................................................................................51Figure 7-36. Device n Status Register...................................................................................................52Figure 7-37. Device n Frame Number Register.....................................................................................54Figure 7-38. Device n SOF/EOP Count Register..................................................................................54Figure 7-39. OTG Registers..................................................................................................................55Figure 7-40. OTG Control Register........................................................................................................55Figure 7-41. GPIO Registers.................................................................................................................56Figure 7-42. GPIO Control Register......................................................................................................57Figure 7-43. GPIO 0 Output Data Register............................................................................................58
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CY7C67200
LIST OF FIGURES (continued)
Figure 7-44. GPIO n Output Data Register............................................................................................59Figure 7-45. GPIO 0 Input Data Register..............................................................................................59Figure 7-46. GPIO 1 Input Data Register..............................................................................................59Figure 7-47. GPIO 0 Direction Register.................................................................................................60Figure 7-48. GPIO 1 Direction Register.................................................................................................60Figure 7-49. HSS Registers...................................................................................................................61Figure 7-50. HSS Control Register........................................................................................................61Figure 7-51. HSS Baud Rate Register...................................................................................................63Figure 7-52. HSS Transmit Gap Register..............................................................................................63Figure 7-53. HSS Data Register............................................................................................................Figure 7-54. HSS Receive Address Register........................................................................................Figure 7-55. HSS Receive Counter Register.........................................................................................65Figure 7-56. HSS Transmit Address Register.......................................................................................65Figure 7-57. HSS Transmit Counter Register........................................................................................66Figure 7-58. HPI Registers....................................................................................................................66Figure 7-59. HPI Breakpoint Register....................................................................................................66Figure 7-60. Interrupt Routing Register.................................................................................................67Figure 7-61. SIEXmsg Register.............................................................................................................69Figure 7-62. HPI Mailbox Register.........................................................................................................69Figure 7-63. HPI Status Port..................................................................................................................70Figure 7-. SPI Registers....................................................................................................................72Figure 7-65. SPI Configuration Register................................................................................................72Figure 7-66. SPI Control Register..........................................................................................................74Figure 7-67. SPI Interrupt Enable Register............................................................................................75Figure 7-68. SPI Status Register...........................................................................................................76Figure 7-69. SPI Interrupt Clear Register..............................................................................................77Figure 7-70. SPI CRC Control Register.................................................................................................77Figure 7-71. SPI CRC Value Register...................................................................................................78Figure 7-72. SPI Data Register..............................................................................................................79Figure 7-73. SPI Transmit Address Register.........................................................................................79Figure 7-74. SPI Transmit Count Register.............................................................................................79Figure 7-75. SPI Receive Address Register..........................................................................................80Figure 7-76. SPI Receive Count Register..............................................................................................80Figure 7-77. UART Registers................................................................................................................81Figure 7-78. UART Control Register......................................................................................................81Figure 7-79. UART Status Register.......................................................................................................82Figure 7-80. UART Data Register..........................................................................................................82Figure 8-1. EZ-OTG Pin Diagram..........................................................................................................83
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LIST OF TABLES
Table 4-1. Interface Options for GPIO Pins ..........................................................................................11Table 4-2. USB Port Configuration Options ..........................................................................................12Table 4-3. USB Interface Pins ..............................................................................................................12Table 4-4. OTG Interface Pins ..............................................................................................................13Table 4-5. UART Interface Pins ............................................................................................................13Table 4-6. I2C EEPROM Interface Pins ...............................................................................................14Table 4-7. SPI Interface Pins ................................................................................................................14Table 4-8. HSS Interface Pins ..............................................................................................................15Table 4-9. HPI Interface Pins ................................................................................................................15Table 4-10. HPI Addressing ..................................................................................................................16Table 4-11. Charge Pump Interface Pins .............................................................................................17Table 4-12. Charge Pump Interface Pins .............................................................................................18Table 4-13. Crystal Pins .......................................................................................................................18Table 4-14. Boot Configuration Interface ..............................................................................................18Table 5-1. wakeup Sources ..................................................................................................................21Table 7-1. Bank Register Example .......................................................................................................24Table 7-2. CPU Speed Definition ..........................................................................................................25Table 7-3. Force Select Definition ........................................................................................................30Table 7-4. Period Select Definition .......................................................................................................31Table 7-5. USB Data Line Pull-Up and Pull-Down Resistors ................................................................33Table 7-6. Port A Force D± State .........................................................................................................34Table 7-7. PID Select Definition ............................................................................................................38Table 7-8. Mode Select Definition .........................................................................................................57Table 7-9. Scale Select Field Definition for SCK Frequency ................................................................73Table 7-10. CRC Mode Definition .........................................................................................................77Table 7-11. UART Baud Select Definition ............................................................................................81Table 9-1. Pin Descriptions ...................................................................................................................84Table 12-1. Crystal Requirements ........................................................................................................86Table 13-1. DC Characteristics..............................................................................................................86Table 13-2. DC Characteristics: Charge Pump ....................................................................................86Table 15-1. Register Summary .............................................................................................................93Table 16-1. Ordering Information ..........................................................................................................97
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CY7C67200
1.0
INTRODUCTION
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG isdesigned to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISCprocessor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable I/O interface block allowinga wide range of interface options.
CY7C67200nRESETControlTimer 0Timer 1WatchdogUART I/FVbus, IDOTGD+,D-USB-AI2CEEPROM I/FHSS I/FHOST/PeripheralUSB PortsSIE1SHARED INPUT/OUTPUT PINSCY1616-bit RISC COREGPIO [24:0]SPI I/FD+,D-USB-ASIE24Kx16 ROMBIOS8Kx16RAMHPI I/FX1X2PLLMobilePowerBoosterGPIOFigure 1-1. Block Diagram
1.1EZ-OTG Features
•Single-chip programmable USB dual role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and two USB ports
•Support for USB OTG protocol
•On-chip 48-MHz 16-bit processor with dynamically switchable clock speed
•Configurable I/O block supporting a variety of I/O options or up to 25 bits of General Purpose I/O (GPIO)
•4K × 16 internal mask ROM containing built-in BIOS that supports a communication-ready state with access to I2C EEPROM interface, external ROM, UART, or USB•8K x 16 internal RAM for code and data buffering
•16-bit parallel host port interface (HPI) with DMA/Mailbox data path for an external processor to directly access all on-chip memory and control on-chip SIEs
•Fast serial port supports from 9600 baud to 2.0 Mbaud•SPI supporting both master and slave•Supports 12-MHz external crystal or clock
•Power consumption: 50 mA operational; 30 mA standby•2.7V to 3.6V power supply voltage•Package option — 48-pin FBGA
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2.0
Typical Applications
EZ-OTG is a very powerful and flexible dual-role USB controller that supports a wide variety of applications. It is primarily intendedto enable USB OTG capability in applications such as:•Cellular phones
•PDAs and pocket PCs
•Video and digital still cameras•MP3 players
•Mass storage devices.
3.0
3.1
3.1.1
Functional Overview
Processor Core
Processor
EZ-OTG has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.3.1.2
Clocking
EZ-OTG requires a 12-MHz source for clocking. Either an external crystal or TTL-level oscillator may be used. EZ-OTG has aninternal PLL that produces a 48-MHz internal clock from the 12-MHz source.3.1.3
Memory
EZ-OTG has a built-in 4K × 16 masked ROM and a 8K × 16 internal RAM. The masked ROM contains the EZ-OTG BIOS. Theinternal RAM can be used for program code or data.3.1.4
Interrupts
EZ-OTG provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are softwareinterrupts.3.1.5
General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-OTG.3.1.6
Power Management
EZ-OTG has one main power-saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.
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4.0
Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with several interface options available. See Table4-1 to understandhow the interfaces share pins and can coexist. Below are some general guidelines:•I2C EEPROM and OTG do not conflict with any interfaces•HPI is mutually exclusive to: HSS, SPI, and UART. Table 4-1. Interface Options for GPIO Pins
GPIO PinsGPIO31GPIO30GPIO29GPIO24GPIO23GPIO22GPIO21GPIO20GPIO19GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
INTnRDnWRnCSA1A0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CTSRTSRXDTXD
MOSISCKnSSIMISO
TXRX
HPI
HSS
SPI
UART
I2CSCL/SDASCL/SDA
OTGIDOTG
4.1USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specificationrequirements for full- and low-speed (high-speed is not supported). In Host mode, EZ-OTG supports two downstream ports, eachsupport control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-OTG supports one peripheral port with eightendpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints1 though 7 support Interrupt, Bulk (up to Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-OTG alsosupports a combination of Host and Peripheral ports simultaneously. EZ-OTG also supports a combination of Host and Peripheralports simultaneously as shown in Table4-2.
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Table 4-2. USB Port Configuration Options
Port Configurations
OTG
OTG + 1 Host
OTG + 1 Peripheral1 Host + 1 Peripheral1 Host + 1 Peripheral
2 Hosts1 Host1 Host2 Peripherals1 Peripheral1 Peripheral
Port 1AOTGOTGOTGHostPeripheralHostHost–PeripheralPeripheral
–
Port 2A–HostPeripheralPeripheralHostHost–HostPeripheral
–Peripheral
4.1.1USB Features
•USB 2.0-compatible for full and low speed•Up to two downstream USB host ports•Up to two upstream USB peripheral ports
•Configurable endpoint buffers (pointer and length), must reside in internal RAM•Up to eight available peripheral endpoints (1 control endpoint)•Supports Control, Interrupt, Bulk, and Isochronous transfers•Internal DMA channels for each endpoint•Internal pull-up and pull-down resistors
•Internal Series termination resistors on USB data lines4.1.2
USB Pins.
Table 4-3. USB Interface Pins
Pin NameDM1ADP1ADM2ADP2A
Pin Number
F2E3C2D3
4.2OTG Interface
EZ-OTG has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTGport has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG isonly supported on USB PORT 1A.
4.2.1OTG Features
•Internal Charge Pump to supply and control VBUS•VBUS Valid Status (above 4.4V)•VBUS Status for 2.4V< VBUS <0.8V•ID Pin Status
•Switchable 2KΩ internal discharge resistor on VBUS•Switchable 500Ω internal Pull-up resistor on VBUS
•Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines
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4.2.2
OTG Pins.
Table 4-4. OTG Interface Pins
Pin NameDM1ADP1AOTGVBUSOTGIDCSwitchACSwitchB
Pin Number
F2E3C1F4D1D2
4.3General Purpose I/O Interface
EZ-OTG has up to 25 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overallnumber of available GPIOs. 4.3.1
GPIO Description
All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins arelatched directly into registers, a single flip-flop.4.3.2
Unused Pin Descriptions
Unused USB pins should be tri-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled lowthrough the internal pull-down resistor.
Unused GPIO pins should be configured as outputs and driven low.
4.4UART Interface
EZ-OTG has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as adevelopment port or for other interface requirements. The UART interface is exposed through GPIO pins.4.4.1UART Features
•Supports baud rates of 900 to 115.2K•8-N-14.4.2
UART Pins.
Table 4-5. UART Interface Pins
Pin Name
TXRX
Pin Number
B5B4
4.5
I2C EEPROM Interface
EZ-OTG provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store applicationspecific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface.The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentationfor additional details on this interface.
4.5.1I2C EEPROM Features
•Supports EEPROMs up to KB (512K bit)•Auto-detection of EEPROM size
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4.5.2
I2C EEPROM Pins.
Table 4-6. I2C EEPROM Interface Pins
Pin NameSCKSDA
LARGE EEPROM
SCKSDA
F3H3Pin Number
H3F3
SMALL EEPROM
4.6Serial Peripheral Interface
EZ-OTG provides a SPI interface for added connectivity. EZ-OTG may be configured as either an SPI master or SPI slave. TheSPI interface can be exposed through GPIO pins or the External Memory port.4.6.1SPI Features
•Master or slave mode operation
•DMA block transfer and PIO byte transfer modes•Full duplex or half duplex data communication•8-byte receive FIFO and 8-byte transmit FIFO
•Selectable master SPI clock rates from 250 KHz to 12 MHz•Selectable master SPI clock phase and polarity•Slave SPI signaling synchronization and filtering•Slave SPI clock rates up to 2 MHz
•Maskable interrupts for block and byte transfer modes
•Individual bit transfer for non-byte aligned serial communication in PIO mode•Programmable delay timing for the active/in-active master SPI clock•Auto or manual control for master mode slave select signal•Complete access to internal memory4.6.2
SPI Pins
The SPI port has a few different pin location options as shown in Table4-7. The pin location is selectable via the GPIO ControlRegister [0xC006].
Table 4-7. SPI Interface Pins
Pin NamenSSISCKMOSIMISO
Pin NumberF6 or C6D5D4C5
4.7High-Speed Serial Interface
EZ-OTG provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to2 Mbaud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking.Complete control of EZ-OTG can be accomplished through this interface via an extensible API and communication protocol. TheHSS interface can be exposed through GPIO pins or the External Memory port.4.7.1HSS Features•8-bit, no parity code
•Programmable baud rate from 9600 baud to 2 Mbaud•Selectable 1- or 2-stop bit on transmit
•Programmable inter-character gap timing for Block Transmit•8-byte receive FIFO•Glitch filter on receive
•Block mode transfer directly to/from EZ-OTG internal memory (DMA transfer)Document #: 38-08014 Rev. *E
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••••
Selectable CTS/RTS hardware signal handshake protocolSelectable XON/XOFF software handshake protocol
Programmable Receive interrupt, Block Transfer Done interruptsComplete access to internal memory
HSS Pins
4.7.2
Table 4-8. HSS Interface Pins
Pin NameCTSRTSRXTX
Pin Number
F6E4E5E6
4.8Host Port Interface (HPI)
EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plusa bidirectional mailbox register for supporting high-level communication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of EZ-OTG can be accomplished through this interface via an extensibleAPI and communication protocol. Other than the HW communication protocols, a host processor has identical control overEZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.4.8.1HPI Features
•16-bit data bus Interface•16 MB/s throughput
•Auto-Increment of address pointer for fast block mode transfers•Direct memory access (DMA) to internal memory•Bidirectional Mailbox register•Byte Swapping
•Complete access to internal memory•Complete control of SIEs through HPI•Dedicated HPI Status Register4.8.2
HPI Pins
Table 4-9. HPI Interface Pins[1, 2]
Pin NameINTnRDnWRnCSA1A0D15D14D13D12D11D10D9D8D7
Pin Number
H4G4H5G5H6F5F6E4E5E6D4D5C6C5B5
Notes:
1.HPI_INT is for the Outgoing Mailbox Interrupt.
2.HPI strobes are negative logic sampled on rising edge.
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Table 4-9. HPI Interface Pins (continued)[1, 2]
D6D5D4D3D2D1D0
B4C4B3A3C3A2B2
The two HPI address pins are used to address one of four possible HPI port registers as shown in Table4-10 below. Table 4-10. HPI Addressing
HPI A[1:0]HPI DataHPI MailboxHPI AddressHPI Status
A10011
A00101
4.9Charge Pump Interface
VBUS for the USB On-The-Go (OTG) port can be produced by EZ-OTG using its built-in charge pump and some externalcomponents. The circuit connections should look similar to the diagram below.
D1CSWITCHAD2CY7C67200CSWITCHBC1OTGVBUSVBUSC2Figure 4-1. Charge Pump
Component details:
•D1 and D2: Schottky diodes with a current rating greater than 60 mA•C1: Ceramic capacitor with a capacitance of 0.1 uF
•C2: Capacitor value should be no more that 6.5 uF since that is the maximum capacitance allowed by the USB OTG spec for a dual-role device. The minimum value of C2 is 1 uF. There are no restrictions on the type of capacitor for C2.
If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left unconnected.4.9.1Charge Pump Features
•Meets OTG Supplement Requirements, see the DC Characteristics: Charge Pump Table13-2.
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4.9.2
Charge Pump Pins
Table 4-11. Charge Pump Interface Pins
Pin NameOTGVBUSCSwitchACSwitchB
Pin Number
C1D1D2
4.10Booster Interface
EZ-OTG has an on-chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuitboosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, andcapacitor. During power down mode, the circuit is disabled to save power. Figure4-2 shows how to connect the booster circuit.
BOOSTVcc L1 2.7V to 3.6V power supply VSWITCH D1 3.3V VCC AVCC C1 Figure 4-2. Power Supply Connection With Booster
Component details:
•L1: Inductor with inductance of 10 uH and a current rating of at least 250 mA•D1: Schottky diode with a current rating of at least 250 mA
•C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 uF.
Figure4-3 shows how to connect the power supply when the booster circuit is not being used.
BOOSTVcc 3.0V to 3.6V power supply VSWITCH VCC AVCC Figure 4-3. Power Supply Connection Without Booster
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4.10.1
Booster Pins.
Table 4-12. Charge Pump Interface Pins
Pin NameBOOSTVccVSWITCH
Pin Number
F1E2
4.11Crystal Interface
The recommended crystal circuit to be used with EZ-OTG is shown in Figure4-4. If an oscillator is used instead of a crystal circuit,connect it to XTALIN and leave XTALOUT unconnected. For further information on the crystal requirements, see Crystal Require-ments Table12-1.
XTALINCY7C67200Y1XTALOUTC1 = 22 pF12MHzParallel ResonantFundamental Mode500uW20-33pf ±5%C2 = 22 pFFigure 4-4. Crystal Interface
4.11.1
Crystal Pins.
Table 4-13. Crystal Pins
Pin NameXTALINXTALOUT
Pin Number
G3G2
4.12Boot Configuration Interface
EZ-OTG can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] atthe time nRESET is deasserted. The table below shows the different boot pin combinations possible. After a reset pin eventoccurs, the BIOS bootup procedure executes for up to 3 ms. GPIO[31:30] are sampled by the BIOS during bootup only. Afterbootup these pins are available to the application as GPIOs. Table 4-14. Boot Configuration Interface
GPIO31 (Pin 39)
0011
GPIO30 (Pin 40)
0101
Boot Mode
Host Port Interface (HPI)High Speed Serial (HSS)
Serial Peripheral Interface (SPI, slave mode)I2C EEPROM (Standalone Mode)
GPIO[31:30] should be pulled high or low as needed using resistors tied to VCC or GND with resistor values between 5KΩ and15KΩ. GPIO[31:30] should not be tied directly to VCC or GND. Note that in Standalone mode, the pull-ups on those two pins areused for the serial I2C EEPROM (if implemented). The resistors used for these pull-ups should conform to the serial EEPROMmanufacturer's requirements.
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If any mode other then standalone is chosen, EZ-OTG will be in coprocessor mode. The device will power up with the appropriatecommunication interface enabled according to its boot pins and wait idle until a coprocessor communicates with it. See the BIOSdocumentation for greater detail on the boot process.
4.13
4.13.1
Operational Modes
Coprocessor Mode
EZ-OTG can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-OTG andis the main processor rather then EZ-OTG’s own 16-bit internal CPU. An external host processor may interface to EZ-OTGthrough one of the following three interfaces in coprocessor mode:
•HPI mode, a 16-bit parallel interface with up to 16MBytes transfer rate•HSS mode, a serial interface with up to 2 MBaud transfer rate•SPI mode, a serial interface with up to 2 Mbits/s transfer rate.
At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. Please refer to Table4-14 fordetails. Bootloading begins from the selected interface after POR + 3 ms of BIOS bootup.4.13.2
Stand-alone Mode
In stand-alone mode, there is no external processor connected to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is themain processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB.Please refer to Table4-14 for booting into stand-alone mode.
After booting into stand-alone mode (GPIO[31:30] = ‘11’), the following pins are affected:•GPIO[31:20] are configured as output pins to examine the EEPROM contents•GPIO[28:27] are enabled for debug UART mode
•GPIO[29] is configured for as OTGID for OTG applications on PORT1A
—If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral—If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host•Ports 1B, 2A, and 2B default as USB peripheral ports•All other pins remain INPUT pins.
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4.13.2.1Minimum Hardware Requirements for Stand-alone Mode – Peripheral Only
Minimum Standalone Hardware Configuration - Peripheral OnlyEZ-OTGCY7C67200VRegVBusD+D-GNDSHIELDBootstrap OptionsVccVcc10k10kGPIO[30]GPIO[31]SCL*SDA*Int. 16k x8Code / DataVCCA0A1A2GNDUp to k x8EEPROMVCCWPSCLSDAReservedXINGND, AGND,BoostGND*Bootloading begins after POR + 3ms BIOS bootup*GPIO[31:30] 31 30Up to 2k x8 SCL SDA>2k x8 to k x8 SDA SCL12MHz22pfVCC, AVCC,BoostVCCDPlusDMinusnRESETResetLogicStandard-Bor Mini-BBootloading FirmwareXOUT*Parallel Resonant22pfFundamental Mode500uW20-33pf ±5%Figure 4-5. Minimum Standalone Hardware Configuration – Peripheral Only
5.0
5.1
Power Savings and Reset Description
Power Savings Mode Description
EZ-OTG has one main power savings mode, Sleep. For detailed information on Sleep mode please see section 5.2.
Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.In addition, EZ-OTG is capable of slowing down the CPU clock speed through the CPU Speed Register [0xC008] without affectingother peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz will reduce the overall current draw by around8mA while reducing it from 48 MHz to 3 MHz will reduce the overall current draw by approximately 15 mA.
5.2Sleep
Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the SleepEnable (bit 1) of the Power Control Register [0xC00A]. During Sleep mode (USB Suspend) the following events and states aretrue:
•GPIO pins maintain their configuration during sleep (in suspend)•External Memory Address pins are driven low•XTALOUT will be turned off•Internal PLL will be turned off
•Firmware should disable the charge pump (OTG Control Register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS will only drop to VCC – (2 schottky diode drops)•Booster circuit will be turned off•USB transceivers will be turned off
•CPU will suspend until a programmable wakeup event.
5.3External (Remote) wakeup Source
There are several possible events available to wake EZ-OTG from Sleep mode as shown in Table5-1. These may also be usedas remote wakeup options for USB applications. Please see the Power Down Control Register [0xC00A] for details.
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Upon wakeup, code will begin executing within 200 ms, the time it takes the PLL to stabilize.Table 5-1. wakeup Sources[3, 4]
wakeup Source(if enabled)USB ResumeOTGVBUSOTGIDHPIHSSSPIIRQ0 (GPIO 24)
Event
D+/D- Signaling
LevelAny EdgeReadRead Read Any Edge
5.4Power-On Reset (POR) Description
The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal start up). A typical application mightutilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respectively.
5.5Reset Pin
The Reset pin is active low and requires a minimum pulse duration of 16 12-MHz clock cycles (1.3 ms). A reset event will restoreall registers to their default POR settings. Code execution will then begin 200 ms later at 0xFF00 with an immediate jump to0xE000, the start of BIOS.
It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs for a testmode. If these pins need to be used as inputs, a series resistor is required (10Ω-48Ω is recommended). Please refer to BIOSdocumentation for addition details.
5.6USB Reset
A USB Reset will affect registers 0xC090 and 0xC0B0, all other registers remain unchanged.
6.0
6.1
Memory Map
Mapping
The EZ-OTG has just over 24 KB of addressable memory mapped from 0x0000 to 0xFFFF. This 24 KB contains both programand data space and is byte addressable. Figure6-1. shows the various memory region address locations.
6.2Internal Memory
Of the internal memory, 15 KB is allocated for user’s program and data code. The lower memory space from 0x0000 to 0x04A2is reserved for interrupt vectors, general purpose registers, USB control registers, the stack, and other BIOS variables. The upperinternal memory space contains EZ-OTG control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to0xFFFF. For more information on the reserved lower memory or the BIOS ROM, please refer to the Programmers documentationand the BIOS documentation.
During development with the EZ-OTG toolset, the lower area of User's space (0x04A4 to 0x1000) should be left available to loadthe GDB stub. The GDB stub is required to allow the toolset debug access into EZ-OTG.
Notes:
3.Read data will be discarded (dummy data).4.HPI_INT will assert on a USB Resume.
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Internal MemoryHW INT's0x0000 - 0x00FF0x0100 - 0x011F0x0120 - 0x013F0x0140 - 0x01480x014A - 0x01FFSW INT'sPrimary RegistersSwap RegistersHPI Int / MailboxLCP VariablesDocument #: 38-08014 Rev. *E0x0200- 0x02FFUSB Registers0x0300- 0x030FSlave Setup Packet0x0310- 0x03FFUSB Slave & OTGBIOS Stack0x0400- 0x04A20x04A4- 0x3FFFUSER SPACE~15K0xC000- 0xC0FFControl Registers0xE000- 0xFFFFBIOSFigure 6-1. Memory Map
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7.0
Registers
Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers ofthis type will have multiple definitions for the same address.
The default register values listed in this data sheet may get altered to some other value during BIOS initialization. Please referto the BIOS documentation for Register initialization information.
7.1Processor Control Registers
There are eight registers dedicated to general processor control. Each of these registers is covered in this section and is summa-rized in Figure7-1.
Register NameCPU Flags RegisterRegister Bank RegisterHardware Revision Register
CPU Speed Register Power Control Register Interrupt Enable Register Breakpoint Register USB Diagnostic Register
Address0xC0000xC0020xC0040xC0080xC00A0xC00E0xC0140xC03C
R/WRR/WRR/WR/WR/WR/WW
Figure 7-1. Processor Control Registers
7.1.1
Bit #FieldRead/WriteDefaultBit #Field
-07
-06...Reserved
-05
-04GlobalInterruptEnable
-0
RX
CPU Flags Register [0xC000] [R]
15
14
13
12
Reserved...
-03NegativeFlag
RX
-02OverflowFlag
RX
-01CarryFlagRX
-00ZeroFlagRX
11
10
9
8
Read/WriteDefault
-0
-0
Figure 7-2. CPU Flags Register
Register Description
The CPU Flags Register is a read-only register that gives processor flags status.Global Interrupt Enable (Bit 4)
The Global Interrupt Enable bit indicates if the Global Interrupts are enabled.1: Enabled 0: Disabled
Negative Flag (Bit 3)
The Negative Flag bit indicates if an arithmetic operation results in a negative answer.1: MS result bit is ‘1’0: MS result bit is not ‘1’Overflow Flag (Bit 2)
The Overflow Flag bit indicates if an overflow condition has occurred. An overflow condition can occur if an arithmetic result waseither larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction.1: Overflow occurred0: Overflow did not occurDocument #: 38-08014 Rev. *E
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Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction. 1: Carry/Borrow occurred0: Carry/Borrow did not occurZero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted in a ‘0’. 1: Zero occurred0: Zero did not occur7.1.2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0R/W07
R/W06...AddressR/W0
R/W0
-X
-X
R/W05
R/W04
Bank Register [0xC002] [R/W]
15
14
13
12
Address...
R/W03
R/W02Reserved
-X
-X
-X
R/W01
R/W10
11
10
9
8
Figure 7-3. Bank Register
Register Description
The Bank Register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registersR0–R15. A register address is automatically generated by:
a.Shifting the four LSBs of the register address left by 1.
b.ORing the four shifted bits of the register address with the 12 MSBs of the Bank Register.c.Force the LSB to zero.
For example, if the Bank Register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will beread. See Table7-1 for details.Table 7-1. Bank Register Example
RegisterBank R14RAM Location
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.Reserved
All reserved bits should be written as ‘0’.
Hex Value0x0100
0x000E << 1 = 0x001C
0x011C
Binary Value0000 0001 0000 00000000 0000 0001 11000000 0001 0001 1100
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7.1.3
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
RX
RX
RX
RX
RX7
RX6
RX5
RX4
...Revision
RX
RX
RX
RX
Hardware Revision Register [0xC004] [R]
15
14
13
12
Revision...
RX3
RX2
RX1
RX0
11
10
9
8
Figure 7-4. Revision Register
Register Description
The Hardware Revision Register is a read only register that indicates the silicon revision number. The first silicon revision isrepresented by 0x0101. This number will be increased by one for each new silicon revision.Revision (Bits [15:0])
The Revision field contains the silicon revision number.7.1.4
CPU Speed Register [0xC008] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-0
-0
-07
-06
...Reserved
-0
-0
R/W1
1
-05
-04
15
14
13
12
Reserved...
-03
-02
CPU SpeedR/W
R/W1
R/W1
-01
-00
11
10
9
8
Figure 7-5. CPU Speed Register
Register Description
The CPU Speed Register allows the processor to operate at a user selected speed. This register will only affect the CPU, all otherperipheral timing is still based on the 48-MHz system clock (unless otherwise noted).CPU Speed (Bits[3:0])
The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table7-2.Table 7-2. CPU Speed Definition
CPU Speed [3:0]
00000001001000110100010101100111100010011010
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Processor Speed
48 MHz/148 MHz/248 MHz/348 MHz/448 MHz/548 MHz/8 MHz/748 MHz/848 MHz/948 MHz/1048 MHz/11
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Table 7-2. CPU Speed Definition (continued)
CPU Speed [3:0]
10111100110111101111
Reserved
All reserved bits should be written as ‘0’.7.1.5
Power Control Register [0xC00A] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15Reserved
-07HPI
Wake Enable
R/W0
-014Host/Device 2Wake Enable
R/W06
Reserved
-013Reserved
-05
12
11
10Reserved
-02
Boost 3VOK
Processor Speed
48 MHz/1248 MHz/1348 MHz/1448 MHz/1548 MHz/16
9HSSWake Enable
R/W01SleepEnableR/W0
8SPI
Wake Enable
R/W00HaltEnableR/W0
Host/Device 1OTGWake EnableWake Enable
R/W04GPI
Wake Enable
R/W0
R/W03Reserved
-0
R0
Figure 7-6. Power Control Register
Register Description
The Power Control Register controls the power-down and wakeup options. Either the sleep mode or the halt mode options canbe selected. All other writable bits in this register can be used as a wakeup source while in sleep mode.Host/Device 2 Wake Enable (Bit 14)
The Host/Device 2 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2 transition. This wakeup from the SIE port does not cause an interrupt to the on-chip CPU.1: Enable wakeup on Host/Device 2 transition.0: Disable wakeup on Host/Device 2 transition.Host/Device 1 Wake Enable (Bit 12)
The Host/Device 1 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1 transition. This wakeupfrom the SIE port does not cause an interrupt to the on-chip CPU.1: Enable wakeup on Host/Device 1 transition0: Disable wakeup on Host/Device 1 transitionOTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wakeup condition to occur on either an OTG VBUS_Valid or OTG ID transition(IRQ20).
1: Enable wakeup on OTG VBUS valid or OTG ID transition0: Disable wakeup on OTG VBUS valid or OTG ID transitionHSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wakeup condition to occur on an HSS Rx serial input transition. The processormay take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causesthe wakeup will be discarded.
1: Enable wakeup on HSS Rx serial input transition0: Disable wakeup on HSS Rx serial input transition
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SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI_nSS input transition. The processormay take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causesthe wakeup will be discarded.
1: Enable wakeup on falling SPI nSS input transition0: Disable SPI_nSS interruptHPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wakeup condition to occur on an HPI interface read.1: Enable wakeup on HPI interface read0: Disable wakeup on HPI interface readGPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition.1: Enable wakeup on GPIO(25:24) transition0: Disable wakeup on GPIO(25:24) transitionBoost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.1: Boost circuit not ok and internal voltage rails are below 3.0V0: Boost circuit ok and internal voltage rails are at or above 3.0VSleep Enable (Bit 1)
Setting this bit to ‘1’ will immediately initiate SLEEP mode. While in SLEEP mode, the entire chip is paused achieving the loweststandby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pumpare all powered down, and the USB transceivers are powered down. All counters and timers are paused but will retain their values.SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution will resume within0.5ms.
1: Enable Sleep Mode0: No FunctionHalt Enable (Bit 0)
Setting this bit to ‘1’ will immediately initiate HALT mode. While in HALT mode, only the CPU is stopped. The internal clock stillruns and all peripherals still operate, including the USB engines. The power savings using HALT is most cases will be minimal,but in applications that are very CPU intensive the incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediatelyfollowing the HALT instruction may get executed before the waking interrupt is serviced (you may want to follow the HALTinstruction with two NOPs).1: Enable Halt Mode0: No FunctionReserved
All reserved bits should be written as ‘0’.
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7.1.6
Bit #Field
Interrupt Enable Register [0xC00E] [R/W]
15
14Reserved
13
12OTGInterruptEnable
-05Out MailboxInterruptEnable
R/W0
R/W04Reserved
11SPIInterruptEnableR/W03UARTInterruptEnableR/W0
10Reserved
9
8
Host/Device 2Host/Device 1InterruptInterruptEnableEnable
R/W01Timer 1InterruptEnableR/W0
R/W00Timer 0InterruptEnableR/W0
Read/WriteDefaultBit #Field
-07HSSInterruptEnableR/W0
-06In MailboxInterruptEnableR/W0
-02GPIOInterruptEnableR/W0
Read/WriteDefault
-1
Figure 7-7. Interrupt Enable Register
Register Description
The Interrupt Enable Register allows control of the hardware interrupt vectors. OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG ID / OTG4.4V Valid hardware interrupt.1: Enable OTG interrupt0: Disable OTG interruptSPI Interrupt Enable (Bit 11)
The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA BlockDone.
1: Enable SPI interrupt0: Disable SPI interrupt
Host/Device 2 Interrupt Enable (Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USBDone, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt0: Disable Host 2 and Device 2 interruptHost/Device 1 Interrupt Enable (Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USBDone, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device1Endpoint n.
1: Enable Host 2 and Device 2 interrupt0: Disable Host 2 and Device 2 interruptHSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done,and HSS RX Full.1: Enable HSS interrupt0: Disable HSS interrupt
In Mailbox Interrupt Enable (Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.1: Enable MBXI interrupt0: Disable MBXI interrupt
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Out Mailbox Interrupt Enable (Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt. 1: Enable MBXO interrupt0: Disable MBXO interruptUART Interrupt Enable (Bit 3)
The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX, and UART RX.1: Enable UART interrupt0: Disable UART interruptGPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General Purpose I/O Pins Interrupt (See the GPIO Control Register). WhenGPIO bit is reset, all pending GPIO interrupts are also cleared.1: Enable GPIO interrupt0: Disable GPIO interruptTimer 1 Interrupt Enable (Bit 1)
The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1interrupts are cleared.1: Enable TM1interrupt0: Disable TM1 interruptTimer 0 Interrupt Enable (Bit 0)
The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0interrupts are cleared.1: Enable TM0 interrupt0: Disable TM0 interruptReserved
All reserved bits should be written as ‘0’.7.1.7
Breakpoint Register [0xC014] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
R/W07
R/W06
R/W05
R/W04
...Address
R/W0
R/W0
R/W0
R/W0
15
14
13
12
Address...
R/W03
R/W02
R/W01
R/W00
11
10
9
8
Figure 7-8. Breakpoint Register
Register Description
The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interruptoccurs. To clear this interrupt, a zero value should be written to this register.Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
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7.1.8
USB Diagnostic Register [0xC03C] [R/W]
Bit #Field
15Reserved
14Port 2ADiagnosticEnableR/W06Pull-downEnableR/W0
13Reserved
12Port 1ADiagnosticEnableR/W04FS Pull-upEnableR/W0
-03Reserved
-0
R/W0-02
11
10
Reserved...
9
8
Read/WriteDefaultBit #FieldRead/WriteDefault
-07...Reserved
-0
-05LS Pull-upEnableR/W0
-01Force Select
R/W0
-00
R/W0
Figure 7-9. USB Diagnostic Register
Register Description
The USB Diagnostic Register provides control of diagnostic modes. It is intended for use by device characterization tests, not fornormal operations. This register is Read/Write by the on-chip CPU but is write only via the HPI port.Port 2A Diagnostic Enable (Bit 15)
The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register.1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD0: Do not apply test conditions Port 1A Diagnostic Enable (Bit 15)
The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register.1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD0: Do not apply test conditions Pull-down Enable (Bit 6)
The Pull-down Enable bit enables or disables full-speed pull-down resistors (pull-down on both D+ and D–) for testing.1: Enable pull-down resistors on both D+ and D–0: Disable pull-down resistors on both D+ and D–LS Pull-up Enable (Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed pull-up resistor (pull-up on D–) for testing.1: Enable low-speed pull-up resistor on D–0: Pull-up resistor is not connected on D–FS Pull-up Enable (Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed pull-up resistor (pull-up on D+) for testing.1: Enable full-speed pull-up resistor on D+0: Pull-up resistor is not connected on D+Force Select (Bits [2:0])
The Force Select field bit selects several different test condition states on the data lines (D+/D–). See Table7-3 for details. Table 7-3. Force Select Definition
Force Select [2:0]
1xx01x001000
Data Line StateAssert SE0Toggle JKAssert JAssert K
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Reserved
All reserved bits should be written as ‘0’.
7.2Timer Registers
There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarizedin Figure7-10.
Register Name
Watchdog Timer Register
Timer 0 Register Timer 1 Register
Figure 7-10. Timer Registers
7.2.1
Watchdog Timer Register [0xC00C] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W07
...ReservedR/W0
R/W0R/W06
R/W05TimeoutFlagR/W0
R/W004
PeriodSelect
R/W0
15
14
13
12
Reserved...R/W
R/W03
R/W02LockEnableR/W0
R/W01WDTEnableR/W0
R/W00ResetStrobeW0
11
10
9
8
Address0xC00C0xC0100xC012R/WR/WR/WR/W
Figure 7-11. Watchdog Timer Register
Register Description
The Watchdog Timer Register provide status and control over the Watchdog timer. The Watchdog timer can also interrupt theprocessor.
Timeout Flag (Bit 5)
The Timeout Flag bit indicates if the Watchdog timer has expired. The processor can read this bit after exiting a reset to determineif a Watchdog time-out occurred. This bit will be cleared on the next external hardware reset.1: Watchdog timer expired0: Watchdog timer did not expirePeriod Select (Bits [4:3])
The Period Select field is defined in Table7-4. If this time expires before the Reset Strobe bit is set, the internal processor willget reset.
Table 7-4. Period Select Definition
Period Select[4:3]
00011011
Lock Enable (Bit 2)
The Lock Enable bit will not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabledpermanently so that it can only be cleared on reset (the WDT Enable bit is ignored).1: Watchdog timer permanently set0: Watchdog timer not permanently setDocument #: 38-08014 Rev. *E
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WDT Period Value
1.4 ms5.5 ms22.0 ms66.0 ms
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WDT Enable (Bit 1)
The WDT Enable bit enables or disables the Watchdog timer.1: Enable Watchdog timer operation0: Disable Watchdog timer operationReset Strobe (Bit 0)
The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoida Watchdog trigger1: Reset CountReserved
All reserved bits should be written as ‘0’.7.2.2Timer n Register [R/W]•Timer 0 Register 0xC010•Timer 1 Register 0xC012
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W1
R/W1
R/W1
R/W1
R/W17
R/W16
R/W15
R/W14
...Count
R/W1
R/W1
R/W1
R/W1
15
14
13
12
Count...
R/W13
R/W12
R/W11
R/W10
11
10
9
8
Figure 7-12. Timer n Register
Register Description
The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1 µs clock tick. Each can providean interrupt to the CPU when the timer reaches zero.Count (Bits [15:0])
The Count field sets the Timer count.
7.3General USB Registers
There is one set of register dedicated to general USB control. This set consists of two identical registers, one for Host/DevicePort 1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is coveredin this section and summarized in Figure7-13. USB Host-only registers are covered in section 7.4 and USB Device-only registersare covered in section 7.5.
Register NameUSB n Control Register
Address (SIE1/SIE2)0xC08A / 0xC0AA
Figure 7-13. USB Registers
7.3.1USB n Control Register [R/W]•USB 1 Control Register 0xC08A•USB 2 Control Register 0xC0AA
R/WR/W
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Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15
Reserved-X
7
Port A
Resistors Enable
R/W0
1413Port AD+ Status
12Port AD– Status
RX
11Reserved
-03
10LOAR/W02SuspendEnableR/W0
1
9ModeSelectR/W0
0
8Reserved
-0
-X
6
RX5
Reserved-0
-0
4
Port AForce D± StateR/W0
R/W0
Reserved
-0
Port A
SOF/EOP Enable
R/W0
Figure 7-14. USB n Control Register
Register Description
The USB n Control Register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USBports. This register can be accessed by the HPI interface.Port A D+ Status (Bit 13)
The Port A D+ Status bit is a read-only bit that indicates the value of DATA+ on Port A.1: D+ is high0: D+ is low
Port A D– Status (Bit 12)
The Port A D– Status bit is a read-only bit that indicates the value of DATA– on Port A.1: D– is high0: D– is lowLOA (Bit 10)
The LOA bit selects the speed of Port A.1: Port A is set to Low speed mode0: Port A is set to Full speed modeMode Select (Bit 9)
The Mode Select bit sets the SIE for host or device operation. When set for device operation only one USB port is supported.The active port is selected by the Port Select bit in the Host n Count Register.1: Host mode0: Device mode
Port A Resistors Enable (Bit 7)
The Port A Resistors Enable bit enables or disables the pull-up/pull-down resistors on Port A. When enabled, the Mode Selectbit and LOA bit of this Register will set the pull-up/pull-down resistors appropriately. When the Mode Select is set for Host mode,the pull-down resistors on the data lines (D+ and D–) are enabled. When the Mode Select is set for Device mode, a single pull-up resistor on either D+ or D–, determined by the LOA bit, will be enabled. Please see Table7-5 for details.1: Enable pull-up/pull-down resistors0: Disable pull-up/pull-down resistors
Table 7-5. USB Data Line Pull-Up and Pull-Down Resistors
L0AXX10
Mode Select
X1
00
Port n Resistors Enable
01
11
Function
Pull-up/Pull-down on D+ and D– DisabledPull-down on D+ and D– EnabledPull-up on USB D– EnabledPull-up on USB D+ Enabled
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Port A Force D± State (Bits [4:3])
The Port A Force D± State field controls the forcing state of the D+ D– data lines for Port A. This field will Force the state of thePort A data lines independent of the Port Select bit setting. See Table7-6 for details.Table 7-6. Port A Force D± StatePort A Force D± State
0011
0101
Function
Normal Operation
Force USB Reset, SE0 StateForce J-State.Force K-State.
Suspend Enable (Bit 2)
The Suspend Enable bit enables or disables the suspend feature on both ports. When suspend is enabled the USB transceiversare powered down and can not transmit or received USB packets but can still monitor for a wakeup condition.1: Enable suspend 0: Disable suspend
Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host mode. In device mode this bit should be written as ‘0’. In host modethis bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs will be generated depending on the LOA bit in theUSB n Control Register when Port A is active.1: Enable SOFs or EOPs0: Disable SOFs or EOPsReserved
All reserved bits should be written as ‘0’.
7.4USB Host Only Registers
There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unlessotherwise noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarizedin Figure7-15.
Register Name
Address (Host 1 / Host 2)
R/W
Host n Control Register Host n Address Register Host n Count Register
Host n Endpoint Status Register
Host n PID Register
Host n Count Result Register Host n Device Address Register Host n Interrupt Enable Register
Host n Status Register
Host n SOF/EOP Count RegisterHost n SOF/EOP Counter Register
Host n Frame Register0xC080 / 0xC0A00xC082 / 0xC0A20xC084 / 0xC0A40xC086 / 0xC0A60xC086 / 0xC0A60xC088 / 0xC0A80xC088 / 0xC0A80xC08C / 0xC0AC0xC090 / 0xC0B00xC092 / 0xC0B20xC094 / 0xC0B40xC096 / 0xC0B6R/WR/WR/WRWRWR/WR/WR/WRR
Figure 7-15. USB Host Only Register
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7.4.1Host n Control Register [R/W]•Host 1 Control Register 0xC080•Host 2 Control Register 0xC0A0
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-07PreambleEnableR/W0
-06SequenceSelectR/W0
-05SyncEnableR/W0
-04ISOEnableR/W0
-0
15
14
13
12
Reserved
-03
-02Reserved
-0
-0-01
-00ArmEnableR/W0
11
10
9
8
Figure 7-16. Host n Control Register
Register Description
The Host n Control Register allows high-level USB transaction control.Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit shouldonly be set when communicating with a low-speed device.1: Enable Preamble packet0: Disable Preamble packetSequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequencechecking must be handled in firmware.1: Send DATA10: Send DATA0Sync Enable (Bit 5)
The Sync Enable bit will synchronize the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.1: The next enabled packet will be transferred after the SOF or EOP packet is transmitted0: The next enabled packet will be transferred as soon as the SIE is freeISO Enable (Bit 4)
The ISO Enable bit enables or disables an Isochronous transaction.1: Enable Isochronous transaction0: Disable Isochronous transactionArm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction iscomplete.
1: Arm endpoint and begin transaction0: Endpoint disarmedReserved
All reserved bits should be written as ‘0’.7.4.2Host n Address Register [R/W]•Host 1 Address Register 0xC082•Host 2 Address Register 0xC0A2
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Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15R/W07R/W0
14R/W06R/W0
13R/W05R/W0
12
Address...R/W04
...AddressR/W0
11R/W03R/W0
10R/W02R/W0
9R/W01R/W0
8R/W00R/W0
Figure 7-17. Host n Address Register
Register Description
The Host n Address Register is used as the base pointer into memory space for the current host transactions.Address (Bits [15:0])
The Address field sets the address pointer into internal RAM or ROM.7.4.3Host n Count Register [R/W]•Host 1 Count Register 0xC084•Host 2 Count Register 0xC0A4
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
-07
-06
-05
15
14
13
Reserved
-04
...Count
R/W0
R/W0
R/W0
R/W0
-03
-02
R/W01
12
11
10
9
Count...
R/W008
Figure 7-18. Host n Count Register
Register Description
The Host n Count Register is used to hold the number of bytes (packet length) for the current transaction. The maximum packetlength is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximumnumber of bytes to receive. If the number of received bytes is greater then the Host Count value then an overflow condition willbe flagged by the Overflow bit in the Host n Endpoint Status Register.Count (Bits [9:0])
The Count field sets the value for the current transaction data packet length. This value is retained when switching between hostand device mode, and back again.Reserved
All reserved bits should be written as ‘0’.7.4.4Host n Endpoint Status Register [R]•Host 1 Endpoint Status Register 0xC086•Host 2 Endpoint Status Register 0xC0A6
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Bit #FieldRead/WriteDefaultBit #Field
1514
Reserved
131211OverflowFlag
10UnderflowFlag
R02TimeoutFlagR0
9
Reserved-01ErrorFlagR0
8
-07StallFlagR0
-06NAKFlagR0
-05LengthExceptionFlag
R0
-04Reserved
R03SequenceStatus
R0
-00ACKFlagR0
Read/WriteDefault
-0
Figure 7-19. Host n Endpoint Status Register
Register Description
The Host n Endpoint Status Register is a read only register that provides status for the last USB transaction. Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in theHost n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the Length ExceptionFlag set to ‘1’.
1: Overflow condition occurred0: Overflow condition did not occurUnderflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specifiedin the Host n Count Register. The Underflow Flag should be checked in response to a Length Exception signified by the LengthException Flag set to ‘1’.1: Underflow condition occurred0: Underflow condition did not occurStall Flag (Bit 7)
The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction.1: Device returned Stall0: Device did not return StallNAK Flag (Bit 6)
The NAK Flag bit indicates that the peripheral device replied with a NAK in the last transaction.1: Device returned NAK0: Device did not return NAKLength Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximumHost Count specified in the Host n Count Register. A Length Exception can either mean an overflow or underflow and the Overflowand Underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred.1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occurSequence Status (Bit 3)
The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoringand handling the sequence status. The Sequence bit is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to ‘0’ whenan error is detected in the transaction and the Error bit will be set.1: DATA10: DATA0
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Timeout Flag (Bit 2)
The Timeout Flag bit indicates if a timeout condition occurred for the last transaction. A timeout condition can occur when a deviceeither takes too long to respond to a USB host request or takes too long to respond with a handshake.1: Timeout occurred0: Timeout did not occurError Flag (Bit 1)
The Error Flag bit indicates a transaction failed for any reason other than the following: Timeout, receiving a NAK, or receiving aSTALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors will result in anError flag along with receiving incorrect packet types.1: Error detected0: No error detectedACK Flag (Bit 0)
The ACK Flag bit indicates two different conditions depending on the transfer type. For non-Isochronous transfers, this bitrepresents a transaction ending by receiving or sending an ACK packet. For Isochronous transfers, this bit represents asuccessful transaction that will not be represented by an ACK packet.
1: For non-Isochronous transfers, the transaction was ACKed. For Isochronous transfers, the transaction was completedsuccessfully.
0: For non-Isochronous transfers, the transaction was not ACKed. For Isochronous transfers, the transaction did not completedsuccessfully.
7.4.5Host n PID Register [W]•Host 1 PID Register 0xC086•Host 2 PID Register 0xC0A6
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
W0
W0
-07
-06
PID Select
W0
W0
W0
-05
-04
15
14
13
12
Reserved
-03
-02W0
-01W0
-00W0
11
10
9
8
Endpoint Select
Figure 7-20. Host n PID Register
Register Description
The Host n PID Register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used in thenext transaction. PID Select (Bits [7:4])
The PID Select field defined as in Table7-7. ACK and NAK tokens are automatically sent based on settings in the Host n ControlRegister and do not need to be written in this register. Table 7-7. PID Select Definition
PID TYPEset-upINOUTSOFPREAMBLE
NAKSTALLDATA0DATA1
Document #: 38-08014 Rev. *E
PID Select [7:4]1101 (D Hex)1001 (9 Hex)0001 (1 Hex)0101 (5 Hex)1100 (C Hex)1010 (A Hex)1110 (E Hex)0011 (3 Hex)1011 (B Hex)
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Endpoint Select (Bits [3:0])
The Endpoint field which allows addressing up to 16 different endpoints.Reserved
All reserved bits should be written as ‘0’.7.4.6Host n Count Result Register [R]•Host 1 Count Result Register 0xC088•Host 2 Count Result Register 0xC0A8
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R0
R0
R0
R0
R07
R06
R05
R04
...Result
R0
R0
R0
R0
15
14
13
12
Result...
R03
R02
R01
R00
11
10
9
8
Figure 7-21. Host n Count Result Register
Register Description
The Host n Count Result Register is a read-only register that contains the size difference in bytes between the Host Count Valuespecified in the Host n Count Register and the last packet received. If an overflow or underflow condition occurs, i.e., the receivedpacket length differs from the value specified in the Host n Count Register, the Length Exception Flag bit in the Host n EndpointStatus Register will be set. The value in this register is only valid when the Length Exception Flag bit is set and the Error Flag bitis not set; both bits are in the Host n Endpoint Status Register.Result (Bits [15:0])
The Result field will contain the differences in bytes between the received packet and the value specified in the Host n CountRegister. If an overflow condition occurs, Result [15:10] will be set to ‘111111’, a 2’s complement value indicating the additionalbyte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count (number ofbytes not used).Reserved
All reserved bits should be written as ‘0’.7.4.7Host n Device Address Register [W]•Host 1 Device Address Register 0xC088•Host 2 Device Address Register 0xC0A8
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-07...Reserved
-0
W0
W0
W0
-06
-05
-04
15
14
13
12
Reserved...
-03AddressW0
W0
W0
W0
-02
-01
-00
11
10
9
8
Figure 7-22. Host n Device Address Register
Register Description
The Host n Device Address Register is a write-only register that contains the USB Device Address that the host wishes tocommunicate with.
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Address (Bits [6:0])
The Address field contains the value of the USB address for the next device that the host is going to communicate with. Thisvalue needs to be written by firmware.Reserved
All reserved bits should be written as ‘0’.7.4.8Host n Interrupt Enable Register [R/W]•Host 1 Interrupt Enable Register 0xC08C•Host 2 Interrupt Enable Register 0xC0AC
Bit #FieldRead/WriteDefaultBit #Field
7Reserved
15
VBUS
Interrupt Enable
R/W0
6
Port A
Wake Interrupt Enable
R/W014ID InterruptEnable
R/W0
-05Reserved
-0
4
Port A Connect
ChangeInterrupt Enable
R/W0
-0
13
12
Reserved
-0
3
-0
2Reserved
11
10
9
SOF/EOPInterrupt Enable
R/W01
0
Done
Interrupt Enable
-0
R/W08Reserved
-0
Read/WriteDefault
-0
-0
-0
Figure 7-23. Host n Interrupt Enable Register
Register Description
The Host n Interrupt Enable Register will allow control over host-related interrupts.
In this register a bit set to ‘1’ enables the corresponding interrupt while ‘0’ disables the interrupt. VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit will enable or disable the OTG VBUS interrupt. When enabled this interrupt will trigger on bothrising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1and is a reservedbit in Host 2.
1: Enable VBUS interrupt0: Disable VBUS interruptID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit will enable or disable the OTG ID interrupt. When enabled this interrupt will trigger on both rising andfalling edge of OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.1: Enable ID interrupt0: Disable ID interrupt
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit will enable or disable the SOF/EOP timer interrupt.1: Enable SOF/EOP timer interrupt0: Disable SOF/EOP timer interruptPort A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit will enable or disable the remote wakeup interrupt for Port A.1: Enable remote wakeup interrupt for Port A0: Disable remote wakeup interrupt for Port A
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Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit will enable or disable the Connect Change interrupt on Port A. This interrupt willtrigger when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).1: Enable Connect Change interrupt0: Disable Connect Change interruptDone Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done will trigger wheneither the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. Thisinterrupt is used for both Port A and Port B.1: Enable USB Transfer Done interrupt0: Disable USB Transfer Done interruptReserved
All reserved bits should be written as ‘0’.7.4.9Host n Status Register [R/W]•Host 1 Status Register 0xC090•Host 2 Status Register 0xC0B0
Bit #FieldRead/WriteDefaultBit #Field
15VBUS Interrupt Flag
R/WX7Reserved
14ID Interrupt
Flag
R/WX6Port AWake Interrupt
Flag
R/WX
-X5Reserved
-X4
Port A Connect
ChangeInterrupt Flag
R/WX
13
12
Reserved
-X3Reserved
-X2Port ASE0StatusR/WX
11
10
9SOF/EOPInterrupt Flag
R/WX1Reserved
8Reserved
-X0DoneInterrupt Flag
R/WX
Read/WriteDefault
-X
-X
-X
-X
Figure 7-24. Host n Status Register
Register Description
The Host n Status Register will provide status information for host operation. Pending interrupts can be cleared by writing a ‘1’ tothe corresponding bit. This register can be accessed by the HPI interface.VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt willtrigger on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Host 1 and is a reserved bit in Host 2.1: Interrupt triggered0: Interrupt did not triggerID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt will trigger onboth the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2.1: Interrupt triggered0: Interrupt did not triggerSOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates the status of the SOF/EOP Timer interrupt. This bit will trigger ‘1’ when the SOF/EOPtimer expires.1: Interrupt triggered0: Interrupt did not trigger
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Port A Wake Interrupt Flag (Bit 6)
The Port A Wake Interrupt Flag bit indicates remote wakeup on PortA1: Interrupt triggered0: Interrupt did not trigger
Port A Connect Change Interrupt Flag (Bit 4)
The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A. This bit will trigger‘1’ on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port A SE0Status bit, it can be determined whether a device was inserted or removed.1: Interrupt triggered0: Interrupt did not triggerPort A SE0 Status (Bit 2)
The Port A SE0 Status bit indicates if Port A is in an SE0 state or not. Together with the Port A Connect change Interrupt Flagbit, it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).1: SE0 condition0: Non-SE0 conditionDone Interrupt Flag (Bit 0)
The Done Interrupt Flag bit indicates the status of the USB Transfer Done interrupt. The USB Transfer Done will trigger wheneither the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout.Thisinterrupt is used for both Port A and Port B.1: Interrupt triggered0: Interrupt did not trigger
7.4.10Host n SOF/EOP Count Register [R/W]•Host 1 SOF/EOP Count Register 0xC092•Host 2 SOF/EOP Count Register 0xC0B2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W1
R/W1
R/W1
R/W0
-0715
Reserved
-06
R/W15
R/W04
...Count
R/W0
R/W0
R/W0
R/W0
R/W13
14
13
12
11
Count...
R/W12
R/W11
R/W00
10
9
8
Figure 7-25. Host n SOF/EOP Count Register
Register Description
The Host n SOF/EOP Count Register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This valueis loaded each time the SOF/EOP counter counts down to zero. The default value set in this register at power-up is 0x2EE0,which will generate a 1-ms time frame. The SOF/EOP counter is a down counter decremented at a 12-MHz rate. When thisregister is read, the value returned is the programmed SOF/EOP count value. Count (Bits [13:0])
The Count field sets the SOF/EOP counter duration.Reserved
All reserved bits should be written as ‘0’.7.4.11Host n SOF/EOP Counter Register [R]•Host 1 SOF/EOP Counter Register 0xC094•Host 2 SOF/EOP Counter Register 0xC0B4
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Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15
Reserved-X7RX
14-X6RX
13RX5RX
12RX4
...CounterRX
11
Counter...RX3RX
10RX2RX
9RX1RX
8RX0RX
Figure 7-26. Host n SOF/EOP Counter Register
Register Description
The Host n SOF/EOP Counter Register contains the current value of the SOF/EOP down counter. This value can be used todetermine the time remaining in the current frame.Counter (Bits [13:0])
The Counter field contains the current value of the SOF/EOP down counter.7.4.12Host n Frame Register [R]•Host 1 Frame Register 0xC096•Host 2 Frame Register 0xC0B6
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R0
R0
R0
R0
-07
-06
15
14
13Reserved
-05
-04
...Frame
R0
R0
R0
R0
-03
R02
12
11
10
9Frame...
R01
R008
Figure 7-27. Host n Frame Register
Register Description
The Host n Frame Register maintains the next frame number to be transmitted (current frame number + 1). This value is updatedafter each SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count Register (Host1:0xC092, Host 2: 0xC0B2).Frame (Bits [10:0])
The Frame field contains the next frame number to be transmitted.Reserved
All reserved bits should be written as ‘0’.
7.5USB Device Only Registers
There are ten sets of USB Device only registers. All sets consist of at least two registers, one for Device Port 1 and one for DevicePort 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for eachDevice Port for a total of 16 registers per set. The USB Device only registers are covered in this section and summarized inFigure7-28.
Register Name
Device n Endpoint n Control RegisterDevice n Endpoint n Address RegisterDevice n Endpoint n Count Register
Address (Device 1/Device 2)
0x02n00x02n20x02n4
R/WR/WR/WR/W
Figure 7-28. USB Device Only Registers
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Register Name
Device n Endpoint n Status RegisterDevice n Endpoint n Count Result Register
Device n Interrupt Enable Register
Device n Address RegisterDevice n Status RegisterDevice n Frame Number RegisterDevice n SOF/EOP Count Register
Address (Device 1/Device 2)
0x02n60x02n8
0xC08C / 0xC0AC0xC08E / 0xC0AE0xC090 / 0xCB00xC092 / 0xC0B20xC094 / 0xC0B4
R/WR/WR/WR/WR/WR/WRW
Figure 7-28. USB Device Only Registers (continued)
7.5.1Device n Endpoint n Control Register [R/W]
•Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]•Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]•Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]•Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]•Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]•Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]•Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]•Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
Bit #FieldRead/WriteDefaultBit #Field
-X7IN/OUTIgnoreEnableR/WX
-X6SequenceSelectR/WX
-X5StallEnableR/WX
-X4ISOEnableR/WX
15
14
13
12
Reserved
-X3NAKInterruptEnableR/WX
-X2DirectionSelectR/WX
-X1Enable
-X0ArmEnableR/WX
11
10
9
8
Read/WriteDefault
R/WX
Figure 7-29. Device n Endpoint n Control Register
Register Description
The Device n Endpoint n Control Register provides control over a single EP in device mode. There are a total of eight endpointsfor each of the two ports. All endpoints have the same definition for their Device n Endpoint n Control Register.IN/OUT Ignore Enable (Bit 6)
The IN/OUT Ignore Enable bit will force endpoint 0 (EP0) to ignore all IN and OUT requests. This bit should be set so that EP0only excepts Set-up packets at the start of each transfer. This bit must be cleared to except IN/OUT transactions. This bit onlyapplies to EP0.
1: Ignore IN/OUT requests0: Do not ignore IN/OUT requestsSequence Select (Bit 6)
The Sequence Select bit will determine whether a DATA0 or a DATA1 will be sent for the next data toggle. This bit has no effecton receiving data packets, sequence checking must be handled in firmware.1: Send a DATA10: Send a DATA0Stall Enable (Bit 5)
The Stall Enable bit will send a Stall in response to the next request (unless it is a set-up request, which are always ACKed). Thisis a sticky bit and will continue to respond with Stalls until cleared by firmware.1: Send Stall0: Do not send Stall
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ISO Enable (Bit 4)
The ISO Enable bit enables and disables an Isochronous transaction. This bit is only valid for EPs 1–7 and has no function for EP0.1: Enable Isochronous transaction0: Disable Isochronous transactionNAK Interrupt Enable (Bit 3)
The NAK Interrupt Enable bit enables and disables the generation of an Endpoint n interrupt when the device responds to thehost with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable Register must also be set. When a NAK issent to the host, the corresponding EP Interrupt Flag in the Device n Status Register will be set. In addition, the NAK Flag in theDevice n Endpoint n Status Register will be set.1: Enable NAK interrupt0: Disable NAK interruptDirection Select (Bit 2)
The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If thedata stage direction is different from what is set in this bit, it will get NAKed and either the IN Exception Flag or the OUT ExceptionFlag will be set in the Device n Endpoint n Status Register. If a set-up packet is received and the Direction Select bit is setincorrectly, the set-up will get ACKed and the Set-up Status Flag will be set (please refer to the set-up bit of the Device n Endpointn Status Register for details).1: OUT transfer (host to device)0: IN transfer (device to host)Enable (Bit 1)
The Enable bit must be set to allow transfers to the endpoint. If Enable is set to ‘0’ then all USB traffic to this endpoint will beignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs will automatically be returned from this endpoint (exceptset-up packets which are always ACKed as long as the Enable bit is set.)1: Enable transfers to an endpoint
0: Do not allow transfers to an endpointArm Enable (Bit 0)
The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete.1: Arm endpoint0: Endpoint disarmedReserved
All reserved bits should be written as ‘0’.
7.5.2Device n Endpoint n Address Register [R/W]
•Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]•Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]•Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]•Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]•Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]•Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]•Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]•Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/WX
R/WX
R/WX
R/WX
R/WX7
R/WX6
R/WX5
R/WX4
...Address
R/WX
R/WX
R/WX
R/WX
15
14
13
12
Address...
R/WX3
R/WX2
R/WX1
R/WX0
11
10
9
8
Figure 7-30. Device n Endpoint n Address Register
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Register Description
The Device n Endpoint n Address Register is used as the base pointer into memory space for the current Endpoint transaction.There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpointn Address Register.Address (Bits [15:0])
The Address field sets the base address for the current transaction on a signal endpoint.7.5.3Device n Endpoint n Count Register [R/W]
•Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]•Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]•Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]•Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]•Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]•Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]•Device n Endpoint 6 Count Register [Device 1: 0x02 Device 2: 0x02E4]•Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/WX
R/WX
R/WX
R/WX
-X7
-X6
-X5
15
14
13
Reserved
-X4
...Count
R/WX
R/WX
R/WX
R/WX
-X3
-X2
R/WX1
12
11
10
9
Count...
R/WX08
Figure 7-31. Device n Endpoint n Count Register
Register Description
The Device n Endpoint n Count Register designates the maximum packet size that can be received from the host for OUTtransfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN tokenfor a single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of thetwo ports. All endpoints have the same definition for their Device n Endpoint n Count Register.Count (Bits [9:0])
The Count field sets the current transaction packet length for a single endpoint.Reserved
All reserved bits should be written as ‘0’.
7.5.4Device n Endpoint n Status Register [R/W]
•Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]•Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]•Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]•Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]•Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]•Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]•Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]•Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]
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Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
1514
Reserved
131211OverflowFlag
10UnderflowFlagR/WX
3SequenceFlagR/WX
2Time-outFlagR/WX
9
OUT
Exception Flag
R/WX
1ErrorFlagR/WX
8
IN
Exception Flag
R/WX0ACKFlagR/WX
-X7StallFlagR/WX
-X6NAKFlagR/WX
-X
5
LengthException Flag
R/WX
-X
4Set-upFlagR/WX
R/WX
Figure 7-32. Device n Endpoint n Status Register
Register Description
The Device n Endpoint n Status Register provides packet status information for the last transaction received or transmitted. Thisregister is updated in hardware and does not need to be cleared by firmware. There are a total of eight endpoints for each of thetwo ports. All endpoints have the same definition for their Device n Endpoint n Status Register.
The Device n Endpoint n Status Register is a memory-based register that should be initialized to 0x0000 before USB Deviceoperations are initiated. After initialization, this register should not be written to again.Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in theDevice n Endpoint n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by theLength Exception Flag set to ‘1’.1: Overflow condition occurred0: Overflow condition did not occurUnderflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specifiedin the Device n Endpoint n Count Register. The Underflow Flag should be checked in response to a Length Exception signifiedby the Length Exception Flag set to ‘1’.1: Underflow condition occurred0: Underflow condition did not occurOUT Exception Flag (Bit 9)
The OUT Exception Flag bit will indicates when the device received an OUT packet when armed for an IN.1: Received OUT when armed for IN0: Received IN when armed for ININ Exception Flag (Bit 8)
The IN Exception Flag bit will indicates when the device received an IN packet when armed for an OUT.1: Received IN when armed for OUT0: Received OUT when armed for OUTStall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the host. 1: Stall packet was sent to the host0: Stall packet was not sentNAK Flag (Bit 6)
The NAK Flag bit indicates that a NAK packet was sent to the host. 1: NAK packet was sent to the host0: NAK packet was not sent
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Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximumEndpoint Count specified in the Device n Endpoint n Count Register. A Length Exception can either mean an overflow orunderflow and the Overflow and Underflow flags (bits 11 and 10, respectively) should be checked to determine which eventoccurred.
1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occur Set-up Flag (Bit 4)
The Set-up Flag bit indicates that a set-up packet was received. In device mode set-up packets get stored at memory location0x0300 for Device 1 and 0x0308 for Device 2. Set-up packets are always accepted regardless of the Direction Select and ArmEnable bit settings as long as the Device n EP n Control Register Enable bit is set.1: Set-up packet was received0: Set-up packet was not receivedSequence Flag (Bit 3)
The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0. This bit has no effect on receivingdata packets, sequence checking must be handled in firmware.1: DATA1 was received0: DATA0 was receivedTime-out Flag (Bit 2)
The Time-out Flag bit indicates whether a time-out condition occurred on the last transaction. On the device side, a time-out canoccur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in apredetermined time. It can also occur if the device does not receive the data stage of an OUT transfer in time.1: Time-out occurred
0: Time-out condition did not occurError Flag (Bit 2)
The Error Flag bit will be set if a CRC5 and CRC16 error occurs, or if an incorrect packet type is received. Overflow and Underfloware not considered errors and do not affect this bit.1: Error occurred0: Error did not occurACK Flag (Bit 0)
The ACK Flag bit indicates whether the last transaction was ACKed.1: ACK occurred0: ACK did not occur
7.5.5Device n Endpoint n Count Result Register [R/W]
•Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]•Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]•Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]•Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]•Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]•Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]•Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]•Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]
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Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15R/WX7R/WX
14R/WX6R/WX
13R/WX5R/WX
12
Result...R/WX4
...ResultR/WX
11R/WX3R/WX
10R/WX2R/WX
9R/WX1R/WX
8R/WX0R/WX
Figure 7-33. Device n Endpoint n Count Result Register
Register Description
The Device n Endpoint n Count Result Register contains the size difference in bytes between the Endpoint Count specified inthe Device n Endpoint n Count Register and the last packet received. If an overflow or underflow condition occurs. i.e. the receivedpacket length differs from the value specified in the Device n Endpoint n Count Register, the Length Exception Flag bit in theDevice n Endpoint n Status Register will be set. The value in this register is only value when the Length Exception Flag bit is setand the Error Flag bit is not set, both bits are in the Device n Endpoint n Status Register.
The Device n Endpoint n Count Result Register is a memory based register that should be initialized to 0x0000 before USBDevice operations are initiated. After initialization, this register should not be written to again.Result (Bits [15:0])
The Result field will contain the differences in bytes between the received packet and the value specified in the Device n Endpointn Count Register. If an overflow condition occurs, Result [15:10] will be set to ‘111111’, a 2’s complement value indicating theadditional byte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count(number of bytes not used).Reserved
All reserved bits should be written as ‘0’.
7.5.6Device n Interrupt Enable Register [R/W]•Device 1 Interrupt Enable Register 0xC08C•Device 2 Interrupt Enable Register 0xC0AC
Bit #Field
15VBUS InterruptEnableR/W07EP7 InterruptEnable
R/W0
14ID InterruptEnable
R/W06EP6 InterruptEnable
R/W0
-05EP5 InterruptEnable
R/W013
Reserved
12
11
SOF/EOP Time-outInterrupt Enable
-04EP4 InterruptEnable
R/W0
R/W03EP3 InterruptEnable
R/W0
2EP2 InterruptEnable
R/W010Reserved
9SOF/EOPInterruptEnableR/W01EP1 InterruptEnable
R/W0
8Reset InterruptEnableR/W00EP0 InterruptEnable
R/W0
Read/WriteDefaultBit #FieldRead/WriteDefault
-0
Figure 7-34. Device n Interrupt Enable Register
Register Description
The Device n Interrupt Enable Register provides control over device related interrupts including eight different endpoint interrupts. VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit will enable or disable the OTG VBUS interrupt. When enabled this interrupt will trigger on bothrising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is areserved bit in Device 2.1: Enable VBUS interrupt0: Disable VBUS interruptDocument #: 38-08014 Rev. *E
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ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit will enable or disable the OTG ID interrupt. When enabled this interrupt will trigger on both rising andfalling edge of OTG ID pin (only supported in Port 1A). This bit is only available for Device 1and is a reserved bit in Device 2.1: Enable ID interrupt0: Disable ID interrupt
SOF/EOP Time-out Interrupt Enable (Bit 11)
The SOF/EOP Time-out Interrupt Enable bit will enable or disable the SOF/EOP Time-out Interrupt. When enabled this interruptwill trigger when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP CountRegister. In addition, the Device n Frame Register counts the number of times the SOF/EOP Timeout Interrupt triggers betweenreceiving SOF/EOPs. 1: SOF/EOP time-out occurred0: SOF/EOP time-out did not occurSOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit will enable or disable the SOF/EOP received interrupt. 1: Enable SOF/EOP Received interrupt0: Disable SOF/EOP Received interruptReset Interrupt Enable (Bit 8)
The Reset Interrupt Enable bit will enable or disable the USB Reset Detected interrupt 1: Enable USB Reset Detected interrupt0: Disable USB Reset Detected interruptEP7 Interrupt Enable (Bit 7)
The EP7 Interrupt Enable bit will enable or disable endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP7 Transaction Done interrupt0: Disable EP7 Transaction Done interruptEP6 Interrupt Enable (Bit 6)
The EP6 Interrupt Enable bit will enable or disable endpoint seven (EP6) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP6 Transaction Done interrupt0: Disable EP6 Transaction Done interruptEP5 Interrupt Enable (Bit 5)
The EP5 Interrupt Enable bit will enable or disable endpoint seven (EP5) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP5 Transaction Done interrupt0: Disable EP5 Transaction Done interruptEP4 Interrupt Enable (Bit 4)
The EP4 Interrupt Enable bit will enable or disable endpoint seven (EP4) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP4 Transaction Done interrupt0: Disable EP4 Transaction Done interrupt
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EP3 Interrupt Enable (Bit 3)
The EP3 Interrupt Enable bit will enable or disable endpoint seven (EP3) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP3 Transaction Done interrupt0: Disable EP3 Transaction Done interruptEP2 Interrupt Enable (Bit 2)
The EP2 Interrupt Enable bit will enable or disable endpoint seven (EP2) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP2 Transaction Done interrupt0: Disable EP2 Transaction Done interruptEP1 Interrupt Enable (Bit 1)
The EP1 Interrupt Enable bit will enable or disable endpoint seven (EP1) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP1 Transaction Done interrupt0: Disable EP1 Transaction Done interruptEP0 Interrupt Enable (Bit 0)
The EP0 Interrupt Enable bit will enable or disable endpoint seven (EP0) Transaction Done interrupt. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK InterruptEnable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.1: Enable EP0 Transaction Done interrupt0: Disable EP0 Transaction Done interruptReserved
All reserved bits should be written as ‘0’.7.5.7Device n Address Register [W]•Device 1 Address Register 0xC08E•Device 2 Address Register 0xC0AE
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-07...Reserved
-0
W0
W0
W0
-06
-05
-04
15
14
13
12
Reserved...
-03AddressW0
W0
W0
W0
-02
-01
-00
11
10
9
8
Figure 7-35. Device n Address Register
Register Description
The Device n Address Register holds the device address assigned by the host. This register initializes to the default address 0at reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address containedin this register will be responded to, all others are ignored.Address (Bits [6:0])
The Address field contains the USB address of the device assigned by the host.Document #: 38-08014 Rev. *E
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Reserved
All reserved bits should be written as ‘0’.7.5.8Device n Status Register [R/W]•Device 1 Status Register 0xC090•Device 2 Status Register 0xC0B0
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15VBUS Interrupt Flag
R/WX7EP7 Interrupt
Flag
R/WX
14ID Interrupt
Flag
R/WX6EP6 Interrupt
Flag
R/WX
-X5EP5 Interrupt
Flag
R/WX
-X4EP4 Interrupt
Flag
R/WX
13
12
Reserved
-X3EP3 Interrupt
Flag
R/WX
-X2EP2 Interrupt
Flag
R/WX
11
10
9SOF/EOPInterrupt Flag
R/WX1EP1 Interrupt
Flag
R/WX
8Reset Interrupt Flag
R/WX0EP0 Interrupt
Flag
R/WX
Figure 7-36. Device n Status Register
Register Description
The Device n Status Register provides status information for device operation. Pending interrupts can be cleared by writing a ‘1’to the corresponding bit. This register can be accessed by the HPI interface.VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt willtrigger on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Device 1 and is a reserved bit in Device 2.1: Interrupt triggered0: Interrupt did not triggerID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt will trigger onboth the rising and falling edge of the OTG ID pin. This bit is only available for Device 1 and is a reserved bit in Device 2.1: Interrupt triggered0: Interrupt did not triggerSOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt has triggered.1: Interrupt triggered0: Interrupt did not triggerReset Interrupt Flag (Bit 8)
The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt has triggered.1: Interrupt triggered0: Interrupt did not triggerEP7 Interrupt Flag (Bit 7)
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) Transaction Done interrupt has triggered. An EPx TransactionDone interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK InterruptEnable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered0: Interrupt did not trigger
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EP6 Interrupt Flag (Bit 6)
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt has triggered. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receiveACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit inthe Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerEP5 Interrupt Flag (Bit 5)
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt has triggered. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receiveACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit inthe Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerEP4 Interrupt Flag (Bit 4)
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt has triggered. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receiveACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit inthe Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerEP3 Interrupt Flag (Bit 3)
The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt has triggered. An EPx TransactionDone interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK InterruptEnable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerEP2 Interrupt Flag (Bit 2)
The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Transaction Done interrupt has triggered. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receiveACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit inthe Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerEP1 Interrupt Flag (Bit 1)
The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Transaction Done interrupt has triggered. An EPx Transaction Doneinterrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receiveACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit inthe Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerEP0 Interrupt Flag (Bit 0)
The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0) Transaction Done interrupt has triggered. An EPx TransactionDone interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK InterruptEnable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.1: Interrupt triggered
0: Interrupt did not triggerReserved
All reserved bits should be written as ‘0’.Document #: 38-08014 Rev. *E
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7.5.9Device n Frame Number Register [R]•Device 1 Frame Number Register 0xC092•Device 2 Frame Number Register 0xC0B2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R0
R0
R0
R0
15SOF/EOPTime-out Flag
R07
R0614
13
SOF/EOP
Time-out Interrupt Counter
R05
R04
...Frame
R0
R0
R0
R0
12
11Reserved
-03
R0210
9Frame...
R01
R008
Figure 7-37. Device n Frame Number Register
Register Description
The Device n Frame Number Register is a read only register that contains the Frame number of the last SOF packet received.This register also contains a count of SOF/EOP Timeout occurrences.SOF/EOP Time-out Flag (Bit 15)
The SOF/EOP Time-out Flag bit indicates when an SOF/EOP Timeout Interrupt occurs.1: An SOF/EOP Time-out interrupt occurred0: An SOF/EOP Time-out interrupt did not occurSOF/EOP Time-out Interrupt Counter (Bits [14:12])
The SOF/EOP Time-out Interrupt Counter field will increment by 1 from 0 to 7 for each SOF/EOP Time-out Interrupt. This fieldresets to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Time-out Interrupt Enable bit in the Devicen Interrupt Enable Register is set.Frame (Bits [10:0])
The Frame field contains the frame number from the last received SOF packet in full speed mode. This field has no function forlow speed mode. If a SOF Timeout occurs, this field will contain the last received Frame number.7.5.10Device n SOF/EOP Count Register [W]•Device 1 SOF/EOP Count Register 0xC094•Device 2 SOF/EOP Count Register 0xC0B4
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R1
R1
R1
R0
-0715
Reserved
-06
R15
R04
...Count
R0
R0
R0
R0
R13
14
13
12
11
Count...
R12
R11
R00
10
9
8
Figure 7-38. Device n SOF/EOP Count Register
Register Description
The Device n SOF/EOP Count Register should be written with the time expected between receiving a SOF/EOPs. If the SOF/EOPcounter expires before an SOF/EOP is received, an SOF/EOP Time-out Interrupt can be generated. The SOF/EOP Time-outInterrupt Enable and SOF/EOP Time-out Interrupt Flag are located in the Device n Interrupt Enable and Status Registers,respectively.
The SOF/EOP count should be set slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decrements ata 12-MHz rate. Therefore in the case of an expected 1-ms SOF/EOP interval, the SOF/EOP count should be set slightly greaterthen 0x2EE0.
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Count (Bits [13:0])
The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 andfor expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly.Reserved
All reserved bits should be written as ‘0’.
7.6OTG Control Registers
Register NameOTG Control Register
AddressC098H
R/WR/W
There is one register dedicated for OTG operation. This register is covered in this section and summarized in Figure7-39.
Figure 7-39. OTG Registers
7.6.1
Bit #Field
OTG Control Register [0xC098] [R/W]
15
Reserved
14
13VBUSPull-upEnable
-06D–Pull-downEnableR/W0
-0R/W05
12ReceiveDisableR/W04Reserved
11Charge Pump
Enable
R/W03
10VBUSDischargeEnableR/W02OTG DataStatus
-0
RX
9D+Pull-upEnableR/W01IDStatusRX
8D–Pull-upEnableR/W00VBUS Valid
Flag
RX
Read/WriteDefaultBit #Field
-07D+Pull-downEnableR/W0
Read/WriteDefault
-0
Figure 7-40. OTG Control Register
Register Description
The OTG Control Register allows control and monitoring over the OTG port on Port1A.VBUS Pull-up Enable (Bit 13)
The VBUS Pull-up Enable bit enables or disables a 500Ω pull-up resistor onto OTG VBus.1: 500Ω pull-up resistor enabled0: 500Ω pull-up resistor disabledReceive Disable (Bit 12)
The Receive Disable bit enables or powers down (disables) the OTG receiver section.1: OTG receiver powered down and disabled0: OTG receiver enabledCharge Pump Enable (Bit 11)
The Charge Pump Enable bit enables or disables the OTG VBus charge pump.1: OTG VBus charge pump enabled0: OTG VBus charge pump disabledVBUS Discharge Enable (Bit 10)
The VBUS Discharge Enable bit enables or disables a 2KΩ discharge pull-down resistor onto OTG VBus.1: 2KΩ pull-down resistor enabled0: 2KΩ pull-down resistor disabled
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D+ Pull-up Enable (Bit 9)
The D+ Pull-up Enable bit enables or disables a pull-up resistor on the OTG D+ data line.1: OTG D+ dataline pull-up resistor enabled0: OTG D+ dataline pull-up resistor disabledD– Pull-up Enable (Bit 8)
The D– Pull-up Enable bit enables or disables a pull-up resistor on the OTG D– data line.1: OTG D– dataline pull-up resistor enabled0: OTG D– dataline pull-up resistor disabledD+ Pull-down Enable (Bit 7)
The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line.1: OTG D+ dataline pull-down resistor enabled0: OTG D+ dataline pull-down resistor disabledD– Pull-down Enable (Bit 6)
The D– Pull-down Enable bit enables or disables a pull-down resistor on the OTG D- data line.1: OTG D– dataline pull-down resistor enabled0: OTG D– dataline pull-down resistor disabledOTG Data Status (Bit 2)
The OTG Data Status bit is a read-only bit and indicates the TTL logic state of the OTG VBus pin.1: OTG VBus is greater than 2.4V0: OTG VBus is less than 0.8V ID Status (Bit 1)
The ID Status bit is a read-only bit that indicates the state of the OTG ID pin on Port A.1: OTG ID Pin is not connected directly to ground (>10kΩ)0: OTG ID Pin is connected directly ground (< 10Ω)VBUS Valid Flag (Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware should wait at least10 µs before this reading this bit.1: OTG VBus is greater then 4.4V0: OTG VBus is less then 4.4VReserved
All reserved bits should be written as ‘0’.
7.7GPIO Registers
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized inFigure7-41. Register Name
GPIO Control RegisterGPIO0 Output Data RegisterGPIO0 Input Data RegisterGPIO0 Direction RegisterGPIO1 Output Data RegisterGPIO1 Input Data RegisterGPIO1 Direction Register
Figure 7-41. GPIO Registers
Address
0xC0060xC01E0xC0200xC0220xC0240xC0260xC028
R/W
R/WR/WRR/WR/WRR/W
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7.7.1
GPIO Control Register [0xC006] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15Write ProtectEnable
R/W07HSSEnableR/W0
14UDR/W06Reserved
-0
R05SPIEnableR/W0
-0
13
Reserved
1211SASEnable
109ModeSelect
8
-04
R/W03Reserved
-0
R/W02
R/W01Interrupt 0Polarity Select
R/W00Interrupt 0EnableR/W0
-0
R/W0
Figure 7-42. GPIO Control Register
Register Description
The GPIO Control Register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupton IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select[10:8] field read-only until a chip reset.1: Enable Write Protect0: Disable Write ProtectUD (Bit 14)
The UD bit routes the Host/Device 1A Port’s transmitter enable status to GPIO[30]. This is for use with an external ESD protectioncircuit when needed.
1: Route the signal to GPIO[30]0: Do not route the signal to GPIO[30]SAS Enable (Bit 11)
The SAS Enable bit, when in SPI mode, will reroute the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9].1: Reroute SPI_nss to GPIO[15]0: Leave SPI_nss on GPIO[9]Mode Select (Bits [10:8])
The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table7-8.Table 7-8. Mode Select Definition Mode Select [10:8]
111110
GPIO ConfigurationReserved
SCAN — (HW) Scan diagnostic. For production test only. Not for normal operation
HPI — Host Port InterfaceReservedReservedReservedReserved
GPIO — General Purpose Input Output
101100011010001000
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HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[15:12]. 1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[15:12] are free for other purposes.SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it will override and route the SPI_nSSI pin to GPIO15.1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes.Interrupt 0 Polarity Select (Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.1: Sets IRQ0 to rising edge0: Sets IRQ0 to falling edgeInterrupt 0 Enable (Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable Register must also be set in order forthis for this interrupt to be enabled.1: Enable IRQ00: Disable IRQ0Reserved
All reserved bits should be written as ‘0’.7.7.2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
GPIO 0 Output Data Register [0xC01E] [R/W]
15GPIO15R/W07GPIO7R/W0
14GPIO14R/W06GPIO6R/W0
13GPIO13R/W05GPIO5R/W0
12GPIO12R/W04GPIO4R/W0
11GPIO11R/W03GPIO3R/W0
10GPIO10R/W02GPIO2R/W0
9GPIO9R/W01GPIO1R/W0
8GPIO8R/W00GPIO0R/W0
Figure 7-43. GPIO 0 Output Data Register
Register Description
The GPIO 0 Output Data Register controls the output data of the GPIO pins. The GPIO 0 Output Data Register controls GPIO15to GPIO0 while the GPIO 1 Output Data Register controls GPIO31 to GPIO19. When read, this register reads back the last datawritten, not the data on pins configured as inputs (see Input Data Register).Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.Reserved
All reserved bits should be written as ‘0’.
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7.7.3
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
GPIO 1 Output Data Register [0xC024] [R/W]
15GPIO31R/W07GPIO23R/W0
14GPIO30R/W06GPIO22R/W0
13GPIO29R/W05GPIO21R/W0
-04GPIO20R/W0
-03GPIO19R/W0
-0
12
11
Reserved
-02
-01Reserved
-0
-0
10
9
8GPIO24R/W00
Figure 7-44. GPIO n Output Data Register
Register Description
The GPIO 1 Output Data Register controls the output data of the GPIO pins. The GPIO 0 Output Data Register controls GPIO15to GPIO0 while the GPIO 1 Output Data Register controls GPIO31 to GPIO19. When read, this register reads back the last datawritten, not the data on pins configured as inputs (see Input Data Register).Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.Reserved
All reserved bits should be written as ‘0’.7.7.4
GPIO 0 Input Data Register [0xC020] [R]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15GPIO15R07GPIO7R0
14GPIO14R06GPIO6R0
13GPIO13R05GPIO5R0
12GPIO12R04GPIO4R0
11GPIO11R03GPIO3R0
10GPIO10R02GPIO2R0
9GPIO9R01GPIO1R0
8GPIO8R00GPIO0R0
Figure 7-45. GPIO 0 Input Data Register
Register Description
The GPIO 0 Input Data Register reads the input data of the GPIO pins. The GPIO 0 Input Data Register reads from GPIO15 toGPIO0 while the GPIO 1 Input Data Register reads from GPIO31 to GPIO19. Every bit represents the voltage of that GPIO pin.7.7.5
GPIO 1 Input Data Register [0xC026] [R]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15GPIO31R07GPIO23R0
14GPIO30R06GPIO22R0
13GPIO29R05GPIO21R0
-04GPIO20R0
-03GPIO19R0
-0
12
11
Reserved
-02
-01Reserved
-0
-0
10
9
8GPIO24R00
Figure 7-46. GPIO 1 Input Data Register
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Register Description
The GPIO 1 Input Data Register reads the input data of the GPIO pins. The GPIO 0 Input Data Register reads from GPIO15 toGPIO0 while the GPIO 1 Input Data Register reads from GPIO31 to GPIO19. Every bit represents the voltage of that GPIO pin.7.7.6
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
GPIO 0 Direction Register [0xC022] [R/W]
15GPIO15R/W07GPIO7R/W0
14GPIO14R/W06GPIO6R/W0
13GPIO13R/W05GPIO5R/W0
12GPIO12R/W04GPIO4R/W0
11GPIO11R/W03GPIO3R/W0
10GPIO10R/W02GPIO2R/W0
9GPIO9R/W01GPIO1R/W0
8GPIO8R/W00GPIO0R/W0
Figure 7-47. GPIO 0 Direction Register
Register Description
The GPIO 0 Direction Register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction Register controlsGPIO15 to GPIO0 while the GPIO 1 Direction Register controls GPIO31 to GPIO19.
When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register isset to ‘0’, the corresponding GPIO data pin becomes an input.Reserved
All reserved bits should be written as ‘0’.7.7.7
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
GPIO 1 Direction Register [0xC028] [R/W]
15GPIO31R/W07GPIO23R/W0
14GPIO30R/W06GPIO22R/W0
13GPIO29R/W05GPIO21R/W0
R/W04GPIO20R/W0
R/W03GPIO19R/W0
R/W0
12
11
Reserved
R/W02
R/W01ReservedR/W0
R/W0
10
9
8GPIO24R/W00
Figure 7-48. GPIO 1 Direction Register
Register Description
The GPIO 1 Direction Register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction Register controlsGPIO15 to GPIO0 while the GPIO 1 Direction Register controls GPIO31 to GPIO19.
When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register isset to ‘0’, the corresponding GPIO data pin becomes an input.Reserved
All reserved bits should be written as ‘0’.
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7.8
HSS Registers
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized inFigure7-49.
Register NameHSS Control RegisterHSS Baud Rate RegisterHSS Transmit Gap Register
HSS Data Register
HSS Receive Address RegisterHSS Receive Length RegisterHSS Transmit Address RegisterHSS Transmit Length Register
Figure 7-49. HSS Registers
7.8.1
Bit #Field
Address 0xC0700xC0720xC0740xC0760xC0780xC07A0xC07C0xC07ER/WR/WR/WR/WR/WR/WR/WR/WR/W
HSS Control Register [0xC070] [R/W]
15HSSEnableR/W07
14RTS
Polarity Select
R/W06
13CTS
Polarity Select
R/W05OneStop BitR/W0
4TransmitReady
R012XOFF
11XOFFEnableR/W03PacketModeSelectR/W0
10CTSEnableR/W02ReceiveOverflowFlagR/W0
9ReceiveInterruptEnableR/W01ReceivePacket Ready
Flag
R0
8DoneInterruptEnableR/W00ReceiveReadyFlagR0
Read/WriteDefaultBit #Field
R0
TransmitReceiveDone Interrupt Done Interrupt
EnableEnable
R/W0
R/W0
Read/WriteDefault
Figure 7-50. HSS Control Register
Register Description
The HSS Control Register provides high-level status and control over the HSS port.HSS Enable (Bit 15)
The HSS Enable bit enables or disables HSS operation.1: Enables HSS operation0: Disables HSS operationRTS Polarity Select (Bit 14)
The RTS Polarity Select bit selects the polarity of RTS.1: RTS is true when LOW0: RTS is true when HIGHCTS Polarity Select (Bit 13)
The CTS Polarity Select bit selects the polarity of CTS.1: CTS is true when LOW0: CTS is true when HIGHXOFF (Bit 12)
The XOFF bit is a read-only bit that indicates if an XOFF has been received. This bit will automatically clear when an XON has
been received.1: XOFF received0: XON received
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XOFF Enable (Bit 11)
The XOFF Enable bit enables or disables XON/XOFF software handshaking.1: Enable XON/XOFF software handshaking0: Disable XON/XOFF software handshakingCTS Enable (Bit 10)
The CTS Enable bit enables or disables CTS/RTS hardware handshaking.1: Enable CTS/RTS hardware handshaking0: Disable CTS/RTS hardware handshakingReceive Interrupt Enable (Bit 9)
The Receive Interrupt Enable bit enables or disables the Receive Ready and Receive Packet Ready interrupts.1: Enable the Receive Ready and Receive Packet Ready interrupts0: Disable the Receive Ready and Receive Packet Ready interruptsDone Interrupt Enable (Bit 8)
The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts.1: Enable the Transmit Done and Receive Done interrupts0: Disable the Transmit Done and Receive Done interruptsTransmit Done Interrupt Flag (Bit 7)
The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt. It will set when a block transmit is finished.To clear the interrupt, a ‘1’ should be written to this bit.1: Interrupt triggered0: Interrupt did not trigger
Receive Done Interrupt Flag (Bit 6)
The Receive Done Interrupt Flag bit indicates the status of the Receive Done Interrupt. It will set when a block transmit is finished.To clear the interrupt, a ‘1’ should be written to this bit.1: Interrupt triggered0: Interrupt did not triggerOne Stop Bit (Bit 5)
The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits mayvary and does not need to be fixed.1: One stop bit0: Two stop bitsTransmit Ready (Bit 4)
The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data fortransmission.
1: HSS transmit FIFO ready for loading0: HSS transmit FIFO not ready for loadingPacket Mode Select (Bit 3)
The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntrinterrupt.
1: Selects Receive Packet Ready as the source0: Selects Receive Ready as the sourceReceive Overflow Flag (Bit 2)
The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a ‘1’ to thisbit.
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Receive Packet Ready Flag (Bit 1)
The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes or not.1: HSS receive FIFO is full 0: HSS receive FIFO is not fullReceive Ready Flag (Bit 0)
The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty or not.1: HSS receive FIFO is not empty (one or more bytes is reading for reading)0: HSS receive FIFO is empty7.8.2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W1
-07
HSS Baud Rate Register [0xC072] [R/W]
15
14Reserved
-06
-05
R/W04
...Baud
R/W0
R/W1
R/W1
R/W1
R/W03
13
12
11
10Baud...R/W02
R/W01
R/W00
9
8
Figure 7-51. HSS Baud Rate Register
Register Description
The HSS Baud Rate Register will set the HSS Baud Rate. At reset, the default value is 0x0017 which will set the baud rate to2.0MHz.Baud (Bits [12:0])
The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This putsa constraint on the Baud Value as follows: (24 – 1) ≤ Baud ≥ (5000 – 1)Reserved
All reserved bits should bit written as ‘0’.7.8.3
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
-07
-06
-05
-04R/W0
HSS Transmit Gap Register [0xC074] [R/W]
15
14
13
12
Reserved
-03R/W1
-02R/W0
-01R/W0
-00R/W1
11
10
9
8
Transmit Gap Select
Figure 7-52. HSS Transmit Gap Register
Register Description
The HSS Transmit Gap Register is only valid in block transmit mode. It allows for a programmable number of stop bits to beinserted thus overwriting the One Stop Bit in the HSS Control Register. The default reset value of this register is 0x0009, equivalentto two stop bits.
Transmit Gap Select (Bits [7:0])
The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) *bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.Document #: 38-08014 Rev. *E
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Reserved
All reserved bits should be written as ‘0’.7.8.4
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/WX
R/WX
R/WX
R/WX
-X7
-X6
-X5
-X4
Data
R/WX
R/WX
R/WX
R/WX
HSS Data Register [0xC076] [R/W]
15
14
13
12
Reserved
-X3
-X2
-X1
-X0
11
10
9
8
Figure 7-53. HSS Data Register
Register Description
The HSS Data Register contains data received on the HSS port (not for block receive mode) when read. This receive data is validwhen the Receive Ready bit of the HSS Control Register is set to ‘1’. Writing to this register will initiate a single byte transfer ofdata. The Transmit Ready Flag in the HSS Control Register should read ‘1’ before writing to this register (this avoids disruptingthe previous/current transmission). Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.Reserved
All reserved bits should be written as ‘0’.7.8.5
HSS Receive Address Register [0xC078] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
R/W07
R/W06
R/W05
R/W04
...Address
R/W0
R/W0
R/W0
R/W0
15
14
13
12
Address...
R/W03
R/W02
R/W01
R/W00
11
10
9
8
Figure 7-54. HSS Receive Address Register
Register Description
The HSS Receive Address Register is used as the base pointer address for the next HSS block receive transfer. Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.
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7.8.6
HSS Receive Counter Register [0xC07A] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
-07
-06
-05
15
14
13
Reserved
-04
...Counter
R/W0
R/W0
R/W0
R/W0
-03
-02
R/W01
12
11
10
9
Counter...
R/W008
Figure 7-55. HSS Receive Counter Register
Register Description
The HSS Receive Counter Register designates the block byte length for the next HSS receive transfer. This register should beloaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decre-mented. When read, this register indicates the remaining length of the transfer.Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. Whenthe transfer is complete this register returns 0x03FF until reloaded.Reserved
All reserved bits should be written as ‘0’.7.8.7
HSS Transmit Address Register [0xC07C] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
R/W07
R/W06
R/W05
R/W04
...Address
R/W0
R/W0
R/W0
R/W0
15
14
13
12
Address...
R/W03
R/W02
R/W01
R/W00
11
10
9
8
Figure 7-56. HSS Transmit Address Register
Register Description
The HSS Transmit Address Register is used as the base pointer address for the next HSS block transmit transfer.Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
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7.8.8
HSS Transmit Counter Register [0xC07E] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
-07
-06
-05
15
14
13
Reserved
-04
...Counter
R/W0
R/W0
R/W0
R/W0
-03
-02
R/W01
12
11
10
9
Counter...
R/W008
Figure 7-57. HSS Transmit Counter Register
Register Description
The HSS Transmit Counter Register designates the block byte length for the next HSS transmit transfer. This register should beloaded with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value isdecremented. When read, this register indicates the remaining length of the transfer.Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. Whenthe transfer is complete this register returns 0x03FF until reloaded.Reserved
All reserved bits should be written as ‘0’.
7.9HPI Registers
There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be address over HPI. Eachof these registers is covered in this section and are summarized in Figure7-58. Register Name
HPI Breakpoint RegisterInterrupt Routing Register
SIE1msg RegisterSIE2msg RegisterHPI Mailbox Register
Address
0x01400x01420x01440x01480xC0C6
Figure 7-58. HPI Registers
7.9.1
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R0
R0
R0
R0
R07
R06
R05
R04
...Address
R0
R0
R0
R0
R/W
RRWWR/W
HPI Breakpoint Register [0x0140] [R]
15
14
13
12
Address...
R03
R02
R01
R00
11
10
9
8
Figure 7-59. HPI Breakpoint Register
Register Description
The HPI Breakpoint Register is a special onchip memory location which the external processor can access using normal HPImemory read/write cycles. This register is read only by the CPU but is read/write by the HPI port. The contents of this registerhave the same effect as the Breakpoint Register [0xC014]. This special Breakpoint Register is used by software debuggers whichinterface through the HPI port instead of the serial port.Document #: 38-08014 Rev. *E
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When the program counter matches the Breakpoint Address, the INT127 interrupt will trigger. To clear this interrupt, a zero valueshould be written to this register.Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.7.9.2
Bit #FieldRead/WriteDefault
Interrupt Routing Register [0x0142] [R]
15VBUS to HPIEnable
R0
14ID to HPIEnable
R0
13SOF/EOP2 to HPI Enable
R0
12SOF/EOP2 to CPU Enable
R1
11SOF/EOP1 to HPI Enable
R0
10SOF/EOP1 to CPU Enable
R1
9Reset2 to HPI
Enable
R0
8HPI Swap 1Enable
R0
Bit #FieldRead/WriteDefault
7Resume2 to HPI Enable
-0
6Resume1 to HPI Enable
-0
5
Reserved-0
43Done2 to HPIEnable
210HPI Swap 0Enable
-0
Done1 to HPIReset1 to HPIEnableEnable
-0
-0
-0
-0
Figure 7-60. Interrupt Routing Register
Register Description
The Interrupt Routing Register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read only by the CPU but is read/write by the HPI port. By setting the appropriate bit to ‘1’, the SIE interruptis routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status Register. The bits in this registerselect where the interrupts are routed. The individual interrupt enable is handled in the SIE interrupt enable register.VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portSOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port. 1: Route signal to HPI port0: Do not route signal to HPI portSOF/EOP2 to CPU Enable (Bit 12)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can berouted to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.1: Route signal to CPU0: Do not route signal to CPUSOF/EOP1 to HPI Enable (Bit 11)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port. 1: Route signal to HPI port0: Do not route signal to HPI port
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SOF/EOP1 to CPU Enable (Bit 10)
The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can berouted to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.1: Route signal to CPU0: Do not route signal to CPUReset2 to HPI Enable (Bit 9)
The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portHPI Swap 1 Enable (Bit 8)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes toHPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significantdata byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].Resume2 to HPI Enable (Bit 7)
The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portResume1 to HPI Enable (Bit 6)
The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portDone2 to HPI Enable (Bit 3)
The Done2 to HPI Enable bit routes the Done interrupt for Host/Device 2 to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portDone1 to HPI Enable (Bit 2)
The Done1 to HPI Enable bit routes the Done interrupt for Host/Device 1 to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portReset1 to HPI Enable (Bit 1)
The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on-chip CPU.1: Route signal to HPI port0: Do not route signal to HPI portHPI Swap 0 Enable (Bit 0)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes toHPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significantdata byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].7.9.3SIEXmsg Register [W]•SIE1msg Register 0x0144•SIE2msg Register 0x0148
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Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15WX7WX
14WX6WX
13WX5WX
12
Data...
WX4
...Data
WX
11WX3WX
10WX2WX
9WX1WX
8WX0WX
Figure 7-61. SIEXmsg Register
Register Description
The SIEXmsg Register allows an interrupt to be generated on the HPI port. Any write to this register will cause the SIEXmsg flagin the HPI Status Port to go high. If the SIEXmsg interrupt enable bit is set, this will also cause an interrupt on the HPI_INTR pin.The SIEXmsg flag is automatically cleared when the HPI port reads from this register.Data (Bits [15:0])
The Data field[15:0] simply needs to have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.7.9.4
HPI Mailbox Register [0xC0C6] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
R/W07
R/W06
R/W05
R/W04
...Message
R/W0
R/W0
R/W0
R/W0
15
14
13
12
Message...
R/W03
R/W02
R/W01
R/W00
11
10
9
8
Figure 7-62. HPI Mailbox Register
Register Description
The HPI Mailbox Register provides a common mailbox between the CY7C67200 and the external host processor.
If enabled, the HPI Mailbox RX Full interrupt will trigger when the external host processor writes to this register. When theCY7C67200 reads this register the HPI Mailbox RX Full interrupt will automatically get cleared.
If enabled, the HPI Mailbox TX Empty interrupt will trigger when the external host processor reads from this register. The HPIMailbox TX Empty interrupt will automatically clear when the CY7C67200 writes to this register.
In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port will assert signaling the externalprocessor that there is data in the mailbox to read. The HPI_INTR signal will de-assert when the external host processor readsfrom this register.Message (Bits [15:0])
The Message field contains the message that the host processor wrote to the HPI Mailbox Register.
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7.9.5
HPI Status Port [] [HPI: R]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
15VBUSFlagRX7Resume2Flag
RX
14IDFlagRX6Resume1Flag
RX
13Reserved
-X5SIE2msg
RX
12SOF/EOP2
Flag
RX4
11Reserved
-X3Done2FlagRX
10SOF/EOP1
Flag
RX2Done1FlagRX
9Reset2FlagRX1Reset1FlagRX
8Mailbox InFlag
RX0Mailbox Out
Flag
RX
SIE1msg
RX
Figure 7-63. HPI Status Port
Register Description
The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits. This registeris not accessible from the on-chip CPU. The additional SIE status bits are provided to aid external device driver firmwaredevelopment, and are not recommended for applications that do not have an intimate relationship with the on-chip BIOS.Reading from the HPI Status Port does not result in a CPU HPI interface memory access cycle. The external host may continu-ously poll this register without degrading the CPU or DMA performance.VBUS Flag (Bit 15)
The VBUS Flag bit is a read-only bit that indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmwareshould wait at least 10 µs before this reading this bit.1: OTG VBus is greater then 4.4V0: OTG VBus is less then 4.4VID Flag (Bit 14)
The ID Flag bit is a read-only bit that indicates the state of the OTG ID pin.SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 2.1: Interrupt triggered0: Interrupt did not triggerSOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 1.1: Interrupt triggered0: Interrupt did not triggerReset2 Flag (Bit 9)
The Reset2 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 2.1: Interrupt triggered0: Interrupt did not triggerMailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read-only bit that indicates if a message is ready in the incoming mailbox. This interrupt clears whenonchip CPU reads from the HPI Mailbox Register.1: Interrupt triggered0: Interrupt did not triggerResume2 Flag (Bit 7)
The Resume2 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 2.1: Interrupt triggered0: Interrupt did not triggerDocument #: 38-08014 Rev. *E
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Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 1.1: Interrupt triggered0: Interrupt did not triggerSIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the CY7C67200 CPU has written to the SIE2msg register. This bit willclear on an HPI read.
1: The SIE2msg register has been written by the CY7C67200 CPU 0: The SIE2msg register has not been written by the CY7C67200 CPUSIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the CY7C67200 CPU has written to the SIE1msg register. This bit willclear on an HPI read.
1: The SIE1msg register has been written by the CY7C67200 CPU 0: The SIE1msg register has not been written by the CY7C67200 CPUDone2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 2. In device modethis read-only bit indicates if an any of the endpoint interrupts occurs on Device 2. Firmware will need to determine which endpointinterrupt occurred.1: Interrupt triggered0: Interrupt did not triggerDone1 Flag (Bit 2)
In host mode the Done 1 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 1. In device modethis read-only bit indicates if an any of the endpoint interrupts occurs on Device 1. Firmware will need to determine which endpointinterrupt occurred.1: Interrupt triggered0: Interrupt did not triggerReset1 Flag (Bit 1)
The Reset1 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1.1: Interrupt triggered0: Interrupt did not triggerMailbox Out Flag (Bit 0)
The Mailbox Out Flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox. This interrupt clears whenthe external host reads from the HPI Mailbox Register.1: Interrupt triggered0: Interrupt did not trigger
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7.10
SPI Registers
Address 0xC0C80xC0CA0xC0CC0xC0CE0xC0D00xC0D20xC0D40xC0D60xC0D80xC0DA0xC0DC0xC0DE
R/WR/WR/WR/WRWR/WR/WR/WR/WR/WR/WR/W
There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in Figure7-. Register Name
SPI Configuration RegisterSPI Control Register
SPI Interrupt Enable RegisterSPI Status Register
SPI Interrupt Clear RegisterSPI CRC Control RegisterSPI CRC ValueSPI Data Register
SPI Transmit Address RegisterSPI Transmit Count RegisterSPI Receive Address RegisterSPI Receive Count Register
Figure 7-. SPI Registers
7.10.1
SPI Configuration Register [0xC0C8] [R/W]
153WireEnableR/W17MasterActive Enable
R0
14PhaseSelectR/W06MasterEnableR/W0
13SCK PolaritySelect
R/W05SSEnableR/W0
R/W1
R/W1
R/W04
03
12
11
Scale SelectR/W
R/W02
SS Delay Select
R/W1
R/W1
R/W1
R/W01
10
9
8Reserved
-00
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
Figure 7-65. SPI Configuration Register
Register Description
The SPI Configuration Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.3Wire Enable (Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation.1: MISO and MOSI data lines are tied together
0: Normal MISO and MOSI Full Duplex operation (not tied together)Phase Select (Bit 14)
The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode.1: Advanced SCK phase0: Delayed SCK phaseSCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.1: Positive SCK polarity0: Negative SCK polarityScale Select (Bits [12:9])
The Scale Select field provides control over the SCK frequency, based on 48 MHz. See Table7-9 for a definition of this field. Thisfield only applies to master mode. Document #: 38-08014 Rev. *E
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Table 7-9. Scale Select Field Definition for SCK Frequency Scale Select [12:9]
0000000100100011010001010110011110001001101010111100110111101111
SCK Frequency
12 MHz8 MHz6 MHz4 MHz3 MHz2 MHz1.5 MHz1 MHz750 KHz500 KHz375 KHz250 KHz375 KHz250 KHz375 KHz250 KHz
Master Active Enable (Bit 7)
The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle. This field only appliesto master mode.
1: Master state machine is active0: Master state machine is idleMaster Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads‘0’, otherwise value will not change.1: Master SPI interface0: Slave SPI interfaceSS Enable (Bit 5)
The SS Enable bit enables or disables the master SS output.1: Enable master SS output
0: Disable master SS output (three-state master SS output, for single SS line in slave mode)SS Delay Select (Bits [4:0])
When the SS Delay Select field is set to ‘00000’ this indicates manual mode. In manual mode SS is controlled by the SS Manualbit of the SPI Control Register. When the SS Delay Select field is set between ‘00001’ to ‘11111’, this value indicates the count inhalf bit times of auto transfer delay for: SS LOW to SCK active, SCK inactive to SS HIGH, SS HIGH time. This field only appliesto master mode.
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7.10.2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
SPI Control Register [0xC0CA] [R/W]
15SCKStrobeW07TransmitEmpty
R1
14FIFOInitW06ReceiveFullR0
R/W013ByteModeR/W05
12Full Duplex
R/W04
Transmit Bit Length
R/W0
R/W0
R/W0
11SSManualR/w03
10ReadEnableR/W02
9TransmitReady
R01
Receive Bit Length
R/w0
R/W08ReceiveData Ready
R10
Figure 7-66. SPI Control Register
Register Description
The SPI Control Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.SCK Strobe (Bit 15)
The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration Register), but notphase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self clearing.1: SCK Strobe Enable0: No FunctionFIFO Init (Bit 14)
The FIFO Init bit will initialize the FIFO and clear the FIFO Error Status bit. This bit is self clearing.1: FIFO Init Enable0: No FunctionByte Mode (Bit 13)
The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation.1: Set PIO (byte mode) operation0: Set DMA (block mode) operationFull Duplex (Bit 12)
The Full Duplex bit selects between full duplex and half duplex operation.
1: Enable full duplex. Full duplex is not allowed and will not set if the 3Wire Enable bit of the SPI Configuration Register is set to ‘1’0: Enable half duplex operationSS Manual (Bit 11)
The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control Register is all zeros and is configuredas master interface. This field only applies to master mode.1: Activate SS, master drives SS line asserted LOW0: Deactivate SS, master drives SS line deasserted HIGHRead Enable (Bit 10)
The Read Enable bit will initiate a read phase for a master mode transfer or set the slave to receive (in slave mode).
1: Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set untilthe read transfer begins.
0: Initiates the write phase for slave operationTransmit Ready (Bit 9)
The Transmit Ready bit is a read-only bit that indicates if the transmit port is ready to empty and ready to be written.1: Ready for data to be written to the port. The transmit FIFO is not full.0: Not ready for data to be written to the portDocument #: 38-08014 Rev. *E
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Receive Data Ready (Bit 8)
The Receive Data Ready bit is a read-only bit that indicates if the receive port has data ready.1: Receive port has data ready to read0: Receive port does not have data readyTransmit Empty (Bit 7)
The Transmit Empty bit is a read-only bit that indicates if the transmit FIFO is empty.1: Transmit FIFO is empty0: Transmit FIFO is not emptyReceive Full (Bit 6)
The Receive Full bit is a read-only bit that indicates if the receive FIFO is full.1: Receive FIFO is full0: Receive FIFO is not fullTransmit Bit Length (Bits [5:3])
The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted. If Transmit Bit Length is ‘000’, a fullbyte will be transmitted. If Transmit Bit Length is ‘001’ to ‘111’, the value indicates the number of bits that will be transmitted.Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a fullbyte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received.7.10.3
SPI Interrupt Enable Register [0xC0CC] [R/W]
15-07
614-0
5...Reserved
-0
-0
-0
-0
-0
13-0
4
12
Reserved...-0
3
-0
2
ReceiveInterrupt Enable
R/W0
-0
1
TransmitInterrupt Enable
R/W0
-0
0
TransferInterrupt Enable
R/W0-0
11
10
9
8
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
Figure 7-67. SPI Interrupt Enable Register
Register Description
The SPI Interrupt Enable Register controls the SPI port.Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit will enable or disable the byte mode receive interrupt (RxIntVal).1: Enable byte mode receive interrupt0: Disable byte mode receive interruptTransmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit will enable or disable the byte mode transmit interrupt (TxIntVal).1: Enables byte mode transmit interrupt0: Disables byte mode transmit interruptTransfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit will enable or disable the block mode interrupt (XfrBlkIntVal).1: Enables block mode interrupt0: Disables block mode interrupt
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Reserved
All reserved bits should be written as ‘0’.7.10.4
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-07FIFO ErrorFlag
R0
-0
-0
-06
-05
-04
SPI Status Register [0xC0CE] [R]
15
14
13
12
Reserved
-03
-02ReceiveInterrupt Flag
-0
-0
R0
-01TransmitInterrupt Flag
R0
-00TransferInterrupt Flag
R0
11
10
9
8
Reserved
Figure 7-68. SPI Status Register
Register Description
The SPI Status Register is a read only register that provides status for the SPI port.FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred. When this bit is set to ‘1’ and the Transmit Emptybit of the SPI Control Register is set to ‘1’, then a Tx FIFO underflow has occurred. Similarly, when set with the Receive Full bitof the SPI Control Register, a Rx FIFO overflow has occured.This bit automatically clear when the SPI FIFO Init Enable bit of theSPI Control register is set.1: Indicates FIFO error0: Indicates no FIFO errorReceive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt has triggered.1: Indicates a byte mode receive interrupt has triggered0: Indicates a byte mode receive interrupt has not triggeredTransmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read only bit that indicates a byte mode transmit interrupt has triggered.1: Indicates a byte mode transmit interrupt has triggered0: Indicates a byte mode transmit interrupt has not triggeredTransfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read only bit that indicates a block mode interrupt has triggered.1: Indicates a block mode interrupt has triggered0: Indicates a block mode interrupt has not triggered
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CY7C67200
7.10.5
SPI Interrupt Clear Register [0xC0D0] [W]
15-07
14-06
13-05
Reserved
-0
-0
-0
-0
-0
-0
12
Reserved-04
-03
-02
-01
-00
11
10
9
8
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
TransmitTransferInterrupt ClearInterrupt Clear
W0
W0
Figure 7-69. SPI Interrupt Clear Register
Register Description
The SPI Interrupt Clear Register is a write-only register that allows the SPI Transmit and SPI Transfer Interrupts to be cleared.Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that will clear the byte mode transmit interrupt. This bit is self clearing.1: Clear the byte mode transmit interrupt0: No function
Transfer Interrupt Clear (Bit 0)
The Transfer Interrupt Clear bit is a write-only bit that will clear the block mode interrupt. This bit is self clearing.1: Clear the block mode interrupt0: No functionReserved
All reserved bits should be written as ‘0’.7.10.6
SPI CRC Control Register [0xC0D2] [R/W]
15
CRC ModeR/W07-0
R/W06-014
13CRCEnableR/W05-0
12CRCClearR/W04
...Reserved-0
-0
-0
-0
-0
11ReceiveCRCR/W03
10One inCRCR02
9Zero inCRCR01
8Reserved...
-00
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
Figure 7-70. SPI CRC Control Register
Register Description
The SPI CRC Control Register provides control over the CRC source and polynomial value.CRC Mode (Bits [15:14)
The CRCMode field selects the CRC polynomial as defined in Table7-10.Table 7-10. CRC Mode DefinitionCRCMode [9:8]
00011011
CRC Polynomial
MMC 16-bit: X^16 + X^12 + X^5 + 1(CCITT Standard)
CRC7 7-bit: X^7+ X^3 + 1MST 16-bit: X^16+ X^15 + X^2 + 1Reserved, 16-bit polynomial 1.
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CY7C67200
CRC Enable (Bit 13)
The CRC Enable bit will enable or disable the CRC operation.1: Enables CRC operation0: Disables CRC operationCRC Clear (Bit 12)
The CRC Clear bit will clear the CRC with a load of all ones. This bit is self clearing and always reads ‘0’.1: Clear CRC with all ones0: No FunctionReceive CRC (Bit 11)
The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in fullduplex mode. This bit is a don’t care in half duplex mode.1: Assigns the receive bit stream0: Assigns the transmit bit streamOne in CRC (Bit 10)
The One in CRC bit is a read-only bit that indicates if the CRC value is all zeros or not.1: CRC value is not all zeros0: CRC value is all zerosZero in CRC (Bit 9)
The Zero in CRC bit is a read-only bit that indicates if the CRC value is all ones or not.1: CRC value is not all ones0: CRC value is all onesReserved
All reserved bits should be written as ‘0’.7.10.7
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W1
R/W1
R/W1
R/W1
R/W17
R/W16
R/W15
R/W14
...CRC
R/W1
R/W1
R/W1
R/W1
SPI CRC Value Register [0xC0D4] [R/W]
15
14
13
12
CRC...
R/W13
R/W12
R/W11
R/W10
11
10
9
8
Figure 7-71. SPI CRC Value Register
Register Description
The SPI CRC Value Register contains the CRC value.CRC (Bits [15:0])
The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7]are invalid in CRC7 mode.
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CY7C67200
7.10.8
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/WX
R/WX
R/WX
R/WX
-X7
-X6
-X5
-X4
Data
R/WX
R/WX
R/WX
R/WX
SPI Data Register [0xC0D6] [R/W]
15
14
13
12
Reserved
-X3
-X2
-X1
-X0
11
10
9
8
Figure 7-72. SPI Data Register
Register Description
The SPI Data Register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIObyte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the ReceiveData Ready bit of the SPI Control Register is set to ‘1’. Writing to this register in PIO byte mode will initiate a transfer of data, thenumber of bits defined by Transmit Bit Length field in the SPI Control Register. Data (Bits [7:0])
The Data field contains data received or to be transmitted on the SPI port.Reserved
All reserved bits should be written as ‘0’.7.10.9
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
R/W07
R/W06
R/W05
R/W04
...Address
R/W0
R/W0
R/W0
R/W0
SPI Transmit Address Register [0xC0D8] [R/W]
15
14
13
12
Address...
R/W03
R/W02
R/W01
R/W00
11
10
9
8
Figure 7-73. SPI Transmit Address Register
Register Description
The SPI Transmit Address Register is used as the base address for the SPI transmit DMA.Address (Bits [15:0])
The Address field sets the base address for the SPI transmit DMA.7.10.10SPI Transmit Count Register [0xC0DA] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
-07
-06
15
14
13Reserved
-05
-04
...Count
R/W0
R/W0
R/W0
R/W0
-03
R/W02
12
11
10
9Count...R/W01
R/W008
Figure 7-74. SPI Transmit Count Register
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CY7C67200
Register Description
The SPI Transmit Count Register designates the block byte length for the SPI transmit DMA transfer.Count (Bits [10:0])
The Count field sets the count for the SPI transmit DMA transfer.Reserved
All reserved bits should be written as ‘0’.
7.10.11SPI Receive Address Register [0xC0DC [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
R/W07
R/W06
R/W05
R/W04
...Address
R/W0
R/W0
R/W0
R/W0
15
14
13
12
Address...
R/W03
R/W02
R/W01
R/W00
11
10
9
8
Figure 7-75. SPI Receive Address Register
Register Description
The SPI Receive Address Register is issued as the base address for the SPI Receive DMA.Address (Bits [15:0])
The Address field sets the base address for the SPI receive DMA.7.10.12SPI Receive Count Register [0xC0DE] [R/W]
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
-07
-06
15
14
13Reserved
-05
-04
...Count
R/W0
R/W0
R/W0
R/W0
-03
R/W02
12
11
10
9Count...R/W01
R/W008
Figure 7-76. SPI Receive Count Register
Register Description
The SPI Receive Count Register designates the block byte length for the SPI receive DMA transfer.Count (Bits [10:0])
The Count field sets the count for the SPI receive DMA transfer.Reserved
All reserved bits should be written as ‘0’.
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CY7C67200
7.11
UART Registers
There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized inFigure7-77.
Register NameUART Control Register UART Status Register UART Data Register
Address 0xC0E00xC0E20xC0E4
Figure 7-77. UART Registers
7.11.1
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-0-07
-06...Reserved
-0
-0-05
-04ScaleSelectR/W0
R/W0
R/WR/WRR/W
UART Control Register [0xC0E0] [R/W]
15
14
13
12
Reserved...
-03
-02BaudSelectR/W1
R/W1-01
-00UARTEnableR/W1
11
10
9
8
Figure 7-78. UART Control Register
Register Description
The UART Control Register enables or disables the UART allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be freedup for general use. This register must also be written to set the baud rate, which is based on a 48-MHz clock.Scale Select (Bit 4)
The Scale Select bit acts as a prescaler that will divide the baud rate by eight.1: Enable prescaler0: Disable prescalerBaud Select (Bits [3:1])
Please refer to Table7-11 for a definition of this field.Table 7-11. UART Baud Select DefinitionBaud Select [3:1]
000001010011100101110111
UART Enable (Bit 0)
The UART Enable bit enables or disables the UART.1: Enable UART
0: Disable UART. This allows GPIO6 and GPIO7 to be used for general use
Baud Rate w/ DIV8 = 0115.2 KBaud57.6 KBaud38.4 KBaud28.8 KBaud19.2 KBaud14.4 KBaud9.6 KBaud7.2 KBaud
Baud Rate w/ DIV8 = 114.4 KBaud7.2 KBaud4.8 KBaud3.6 KBaud2.4 KBaud1.8 KBaud1.2 KBaud0.9 KBaud
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Reserved
All reserved bits should be written as ‘0’.7.11.2
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
-0
-0
-0
-07
6-0
5
...Reserved
-0
-0
-0
-0
4-0
3
UART Status Register [0xC0E2] [R]
15
14
13
12
Reserved...
-0
2
-0
1Receive Full
R0
-0
0Transmit Full
R0-0
11
10
9
8
Figure 7-79. UART Status Register
Register Description
The UART Status Register is a read-only register that indicates the status of the UART buffer.Receive Full (Bit 1)
The Receive Full bit indicates whether the receive buffer is full. It can be programmed to interrupt the CPU as interrupt #5 whenthe buffer is full. This can be done though the UART bit of the Interrupt Enable Register (0xC00E). This bit will automatically becleared when data is read from the UART Data Register. 1: Receive buffer full0: Receive buffer emptyTransmit Full (Bit 0)
The Transmit Full bit indicates whether the transmit buffer is full or not. It can be programmed to interrupt the CPU as interrupt#4 when the buffer is empty. This can be done though the UART bit of the Interrupt Enable Register (0xC00E). This bit willautomatically be set to ‘1’ after data is written by EZ-Host to the UART Data Register (to be transmitted). This bit will automaticallybe cleared to ‘0’ after the data is transmitted.1: Transmit buffer full (transmit busy)
0: Transmit buffer is empty and ready for a new byte of data7.11.3
Bit #FieldRead/WriteDefaultBit #FieldRead/WriteDefault
R/W0
R/W0
R/W0
R/W0
-07
-06
-05
-04
Data
R/W0
R/W0
R/W0
R/W0
UART Data Register [0xC0E4] [R/W]
15
14
13
12
Reserved
-03
-02
-01
-00
11
10
9
8
Figure 7-80. UART Data Register
Register Description
The UART Data Register contains data to be transmitted or received from the UART port. Data written to this register will start adata transmission and also causes the UART Transmit Empty Flag of the UART Status Register to set. When data received onthe UART port is read from this register, the UART Receive Full Flag of the UART Status Register will get cleared.Data (Bits [7:0])
The Data field is where the UART data to be transmitted or received is locatedReserved
All reserved bits should be written as ‘0’.Document #: 38-08014 Rev. *E
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CY7C67200
8.0
Pin Diagram
CY7C67200 48-pin FBGA
A1A2A3A4A5A6GNDGPIO1/D1
GPIO3/D3
VCCnRESET
Reserved
B1B2B3B4
B5
B6AGND
GPIO0/D0
GPIO4/D4
GPIO6/D6/RX
GPIO7/D7/TX
GND
C1C2C3C4C5
C6
OTGVBUS
DM2AGPIO2/D2
GPIO5/D5
GPIO8/D8/GPIO9/D9/MISO
nSSI
D1D2D3D4D5
D6CSWITCHA
CSWITCHB
DP2AGPIO11/D1/GPIO10/D10/VCCMOSI
SCK
E1E2E3E4E5
E6
BOOSTGND
VSWITCHDP1AGPIO14/D14/GPIO13/D13/GPIO12/D12/RTS
RXD
TXD
F1F2F3
F4F5
F6BOOSTVCC
DM1AGPIO30/SDA
GPIO29/GPIO19/A0
GPIO15/D15/ OTGID
CTS/nSSI
G1G2G3G4
G5
G6AVCCXTALOUT
XTALIN
GPIO23/nRD/GPIO21/nCS/GNDnWAIT
nRESET
H1H2H3
H4
H5
H6
GND
VCC
GPIO31/SCL
GPIO24/INT/GPIO22/nWR
GPIO20/A1
IRQ0
Figure 8-1. EZ-OTG Pin Diagram
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CY7C67200
9.0
Pin Descriptions
Pin NameH3GPIO31/SCKF3F4GPIO30/SDAGPIO29/OTGIDTypeI/OI/OI/ODescriptionGPIO31: General Purpose I/OSCK: I2C EEPROM SCK
GPIO30: General Purpose I/OSDA: I2C EEPROM SDA
GPIO29: General Purpose I/OOTGID: Input for OTG ID pin. When used as OTGID, this pin should be tied high through an external pull-up resistor. Assuming VCC = 3.0V, a 10K to 40K resistor should be used.GPIO24: General Purpose I/OINT: HPI INT
IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one of two possible GPIO wakeup sources.GPIO23: General Purpose I/OnRD: HPI nRD
GPIO22: General Purpose I/OnWR: HPI nWR
GPIO21: General Purpose I/OnCS: HPI nCS
GPIO20: General Purpose I/OA1: HPI A1
GPIO19: General Purpose I/OA0: HPI A0
GPIO15: General Purpose I/OD15: D15 for HPI CTS: HSS CTSnSSI: SPI nSSI
GPIO14: General Purpose I/OD14: D14 for HPI RTS: HSS RTS
GPIO13: General Purpose I/OD13: D13 for HPI
RXD: HSS RXD (Data is received on this pin)GPIO12: General Purpose I/OD12: D12 for HPI
TXD: HSS TXD (Data is transmitted from this pin)GPIO11: General Purpose I/OD11: D11 for HPI MOSI: SPI MOSI
GPIO10: General Purpose I/OD10: D10 for HPI SCK: SPI SCK
GPIO9: General Purpose I/OD9: D9 for HPI nSSI: SPI nSSI
GPIO8: General Purpose I/OD8: D8 for HPI MISO: SPI MISO
GPIO7: General Purpose I/OD7: D7 for HPI
TX: UART TX (Data is transmitted from this pin)GPIO6: General Purpose I/OD6: D6 for HPI
RX: UART RX (Data is received on this pin)
Table 9-1. Pin Descriptions
H4GPIO24/INT/IRQ0I/OG4H5G5H6F5F6GPIO23/nRDGPIO22/nWRGPIO21/nCSGPIO20/A1GPIO19/A0GPIO15/D15/CTS/nSSI
I/OI/OI/OI/OI/OI/OE4GPIO14/D14/RTSI/O
E5GPIO13/D13/RXDI/OE6GPIO12/D12/TXDI/O
D4GPIO11/D11/MOSII/OD5GPIO10/D10/SCKI/O
C6GPIO9/D9/nSSII/OC5GPIO8/D8/MISOI/O
B5GPIO7/D7/TXI/OB4GPIO6/D6/RXI/O
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CY7C67200
Table 9-1. Pin Descriptions (continued)
Pin NameC4GPIO5/D5B3A3C3A2B2F2E3C2D3G3G2A5A6F1E2E1C1D1D2G1B1H2, D6, A4G6, B6, A1, H1GPIO4/D4GPIO3/D3GPIO2/D2GPIO1/D1GPIO0/D0DM1ADP1ADM2ADP2AXTALINXTALOUTnRESETReservedBOOSTVCCVSWITCHBOOSTGNDOTGVBUSCSWITCHACSWITCHBAVCCAGNDVCCGNDDescriptionGPIO5: General Purpose I/OD5: D5 for HPI
I/OGPIO4: General Purpose I/OD4: D4 for HPI
I/OGPIO3: General Purpose I/OD3: D3 for HPI
I/OGPIO2: General Purpose I/OD2: D2 for HPI
I/OGPIO1: General Purpose I/O
D1: D1 for HPI
I/OGPIO0: General Purpose I/OD0: D0 for HPI
I/OUSB Port 1A D–I/OUSB Port 1A D+I/OUSB Port 2A D–I/OUSB Port 2A D+InputCrystal Input or Direct Clock InputOutputCrystal output. Leave floating if direct clock source is used.InputReset–Tie to Gnd for normal operation.PowerBooster Power Input: 2.7V to 3.6VAnalog OutputBooster Switching OutputGroundBooster GroundAnalog I/OUSB OTG VbusAnalogCharge Pump CapacitorAnalogCharge Pump CapacitorPowerUSB PowerGroundUSB GroundPowerMain VccGroundMain GroundTypeI/O10.0 Absolute Maximum Ratings
This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device.Exposure to maximum rated conditions for extended periods can affect device operation and reliability.Storage Temperature..................................–40°C to +125°CAmbient Temperature with Power Supplied..–40°C to +85°CSupply Voltage to Ground Potential.................0.0V to +3.6VDC Input Voltage to Any General Purpose Input Pin..... 5.5VDC Voltage Applied to XTALIN............. –0.5V to VCC + 0.5VStatic Discharge Voltage.......................................... > 2000V Max Output Current, per I/O......................................... 4 mA
11.0 Operating Conditions
TA (Ambient Temperature Under Bias).........–40°C to +85°CSupply Voltage (VCC, AVCC)..........................+3.0V to +3.6VSupply Voltage (BoostVCC)[5].........................+2.7V to +3.6VGround Voltage..................................................................0VFOSC (Oscillator or Crystal Frequency)....12 MHz ± 500 ppm...................................................................Parallel Resonant
Note:
5.The on-chip voltage booster circuit boosts BoostVCC to provide a nominal 3.3V VCC supply.
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CY7C67200
12.0
Crystal Requirements (XTALIN, XTALOUT)
Min.–50020
Typical12
+500335005Max.
UnitMHzPPMpFµWms
Table 12-1. Crystal Requirements
Crystal Requirements, (XTALIN, XTALOUT) Parallel Resonant FrequencyFrequency StabilityLoad CapacitanceDriver LevelStart-up Time
Mode of Vibration: Fundamental
13.0 DC Characteristics
Description
Supply VoltageSupply VoltageInput HIGH VoltageInput LOW VoltageInput Leakage CurrentOutput Voltage HIGHOutput LOW VoltageOutput Current HIGHOutput Current LOWInput Pin CapacitanceHysteresis on nReset PinSupply Current Sleep Current
2 transceivers poweredUSB Peripheral: includes 1.5K internal pull-up
Without 1.5K internal pull-up
Supply Current with Booster Enabled2 transceivers powered
Except D+/D–D+/D–
250
8013521052105
1001805003050030
0< VIN < VCCIOUT = 4 mAIOUT = –4 mA
–10.02.4
0.4441015
Conditions
Min.3.02.72.0
Typ.3.3
Max.3.63.65.50.8+10.0
UnitVVVVµAVVmAmApFpFmVmAmAµAµAµAµA
Table 13-1. DC Characteristics[6]ParameterVCC, AVCCBoosVCCVIHVILIIVOHVOLIOHIOLCINVHYSICC
[7, 8]ICCB[7, 8]ISLEEP
ISLEEPB
Sleep Current with Booster EnabledUSB Peripheral: includes 1.5K
internal pull-up
Without 1.5K internal pull-up
Table 13-2. DC Characteristics: Charge Pump
ParameterVA_VBUS_OUTTA_VBUS_RISEIA_VBUS_OUTCDRD_VBUSVA_VBUS_LKGVDRD_DATA_LKG
Description
Regulated OTGVBUS VoltageVBUS Rise TimeMaximum Load CurrentOUTVBUS Bypass CapacitanceOTGVBUS Leakage VoltageDataline Leakage Voltage
4.4V< VBUS < 5.25VOTGVBUS not driven
Conditions
8 mA< ILOAD < 10 mAILOAD = 10 mA
81.0Min.4.4
Typ.
Max.5.25100106.5200342
UnitVmsmApFmVmV
Notes:
6.All tests were conducted with Charge pump off.
7.ICC and ICCB values are the same regardless of USB host or peripheral configuration.
8.There is no appreciable difference in ICC and ICCB values when only one transceiver is powered.
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CY7C67200
Table 13-2. DC Characteristics: Charge Pump (continued)
ParameterICHARGEICHARGEBIB_DSCHG_INVA_VBUS_VALIDVA_SESS_VALIDVB_SESS_VALIDVA_SESS_ENDERPDRA_BUS_INRB_SRP_UPRB_SRP_DWN
Description
Charge Pump Current Draw
Conditions
ILOAD = 8 mAILOAD = 0 mA
Charge Pump Current Draw with ILOAD = 8 mABooster Active
ILOAD = 0 mAB-Device (SRP Capable) Discharge CurrentA-Device VBUS ValidA-Device Session ValidB-Device Session ValidB-Device Session EndEfficiency When LoadedData Line Pull-down
A-device VBUS Input Impedance VBUS is not being drivento GND
B-device VBUS SRP Pull-upB-device VBUS SRP Pull-down
Pull-up voltage = 3.0VILOAD = 8 mA, VCC = 3.3V
14.2540281656
0V< VBUS < 5.25V
4.40.80.80.2
75
24.81002.04.00.8
Min.
Typ.200300
Max.2014558
UnitmAmAmAmAmAVVVV%ΩkΩΩΩ
13.1USB Transceiver
USB 2.0-compatible in full- and low-speed modes.
14.0
14.1
AC Timing Characteristics
Reset Timing tRESETnRESETtIOACTnRD or nWRL or nWRHReset TimingParametertRESETtIOACT
Description
nRESET pulse widthnRESET HIGH to nRD or nWRx active
Min.16200
Typ.
Max.
Unitclocks[9]µs
Note:
9.Clock is 12 MHz nominal.
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CY7C67200
14.2
Clock Timing tCLKXTALINtHIGHtLOWtFALLtRISEClock TimingParameterfCLK
vXINH[10]tCLKtHIGHtLOWtRISEtFALL
Duty CycleDescriptionClock frequencyClock input high(XTALOUT left floating)Clock period Clock high timeClock low timeClock rise timeClock fall timeMin.1.583.173636Typ.12.03.0Max.3.683.544445.05.055UnitMHzV83.3345nsnsnsnsns%14.3I2C EEPROM Timing 1. I2C EEPROM Bus Timing - Serial I/OtLOWtHIGHtRtFSCLtSU.STAtHD.STAtHD.DATtSU.DATtSU.STOtBUFSDA INtAAtDHSDA OUTParameterDescriptionMin.TypicalMax.400
UnitkHznsnsnsnsnsnsnsnsnsnsnsns
fSCLtLOWtHIGHtAAtBUFtHD.STAtSU.STAtHD.DATtSU.DATtRtF
tSU.STOtDH
Clock Frequency
Clock Pulse Width LowClock Pulse Width HighClock Low to Data Out ValidBus Idle Before New TransmissionStart Hold TimeStart Set-up TimeData In Hold TimeData In Set-up TimeInput Rise TimeInput Fall TimeStop Set-up TimeData Out Hold Time
130060090013006006000100
300300
6000
Note:
10.vXINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock.
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CY7C67200
14.4HPI (Host Port Interface) Write Cycle Timing tCYCtASUtWPtAHADDR [1:0]tCSSUtCSH nCSnWR nRDDout [15:0]tDSUtWDHParameterDescriptionMin.TypicalMax.Unit
tASUtAHtCSSUtCSHtDSUtWDHtWPtCYC
Address set-upAddress hold Chip select set-upChip select holdData set-upWrite data holdWrite pulse widthWrite cycle time
–1–1–1–1622 6
nsnsnsnsnsnsT[11]T[11]Note:
11.T = system clock period = 1/48 MHz.
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CY7C67200
14.5HPI (Host Port Interface) Read Cycle Timing tCYCtASUtRPtAHADDR [1:0]tCSSUtCSH nCSnWRtRDH nRDDin [15:0]tACCtRDHParameterDescriptionMin.Typ.Max.Unit
tASUtAHtCSSUtCSHtACCtRDHtRPtCYC
Address set-upAddress hold Chip select set-upChip select hold
Data access time, from HPI_nRD falling
Read data hold, relative to the earlier of HPI_nRD rising or HPI_nCS risingRead pulse widthRead cycle time
–1–1–1–1
1
026
7
nsnsnsnsT[11]nsT[11]T[11]Document #: 38-08014 Rev. *EPage 90 of 98
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CY7C67200
14.6
qt_clkCPU_A[2:0]CPUHSS_csCPU_wrTxRdy flagHSS_TxDstart bitbit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7stop bitstart bitBTBTCPU may start another BYTEtransmit right after TxRdygoes highHSS BYTE Mode Transmit
Byte transmittriggered by aCPU write to theHSS_TxData registerTxRdy low to start bit delay:0 min, BT max when starting from IDEL.For back to back transmit, new START Bitbegins immediately following previous STOP bit.(BT = bit period)start of last data bit to TxRdy high:0 min, 4 T max.(T is qt_clk period)programmable1 or 2 stop bits.1 stop bit shown.qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera-tions and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.BT = bit time = 1/baud rate.
14.7HSS Block Mode Transmit
BTHSS_TxDtGAPBLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.The BLOCK mode STOP bit time, tGAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSSTransmit Gap Register 90xC074].The default tGAP is 2 BT.BT = bit time = 1/baud rate.
14.8HSS BYTE and BLOCK Mode Receive
BT +/- 5%BT +/- 5%received byte added toreceive FIFO during the final data bit timeHSS_RxDstart bitbit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7stop bitstart bit10 BT +/- 5%Receive data arrives asynchronously relative to the internal clock.
Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 orhigher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.BT = bit time = 1/baud rate.
Document #: 38-08014 Rev. *EPage 91 of 98
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CY7C67200
14.9
Hardware CTS/RTS Handshake
tCTSholdtCTSsetupHSS_RTSHSS_CTSHSS_TxDStart of transmission delayed until HSS_CTS goes highStart of transmission not delayed by HSS_CTStCTSsetuptCTSholdtCTSset-up: HSS_CTS set-up time before HSS_RTS = 1.5T min.tCTShold: HSS_CTS hold time after START bit = 0 ns min.T = 1/48 MHz.
When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T beforeHSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.HSS_RTS is deasserted in the third data bit time.
An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.
Document #: 38-08014 Rev. *EPage 92 of 98
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CY7C67200
15.0
R/WRR
Register Summary
AddressRegister0x01400x0142
HPI BreakpointInterrupt Routing
Bit 15Bit 7Address......AddressVBUS to HPIEnableResume2 to HPI Enable
ID to HPIEnableResume1 to HPI Enable
SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPIHPI Swap 1HPI EnableCPU EnableHPI EnableCPU EnableEnableEnableReserved
Done2 to HPIDone1 to HPIReset1 to HPIHPI Swap 0
EnableEnableEnableEnable
Bit 14Bit 6
Bit 13Bit 5
Bit 12Bit 4
Bit 11Bit 3
Bit 10Bit 2
Bit 9Bit 1
Bit 8Bit 0
Default HighDefault Low0000 00000000 00000001 01000000 0000xxxx xxxxxxxx xxxxxxxx xxxx
Stall
Enable
ISOEnable
NAK Interrupt DirectionEnableSelect
Enable
ARM
Enable
xxxx xxxxxxxx xxxxxxxx xxxx
Count...
OverflowFlag
NAKFlag
LengthSet-upException FlagFlag
SequenceStatus
UnderflowFlagTimeoutFlag
xxxx xxxxxxxx xxxx
OUTINxxxx xxxxException FlagException FlagErrorFlag
ACKFlag
xxxx xxxxxxxx xxxxxxxx xxxx0000 0000
Global Inter-rupt Enable
Negative FlagReserved
OverflowFlag
CarryFlag
ZeroFlag
000x xxxx0000 0001000x xxxxxxxx xxxxxxxx xxxx
UDReserved
ReservedSPIEnable
Reserved
SASEnable
ModeSelect
Interrupt 0Interrupt 0Polarity SelectEnable
CPU Speed
Host/Device 2ReservedWake Enable
Host/Device 1OTGReservedWake EnableWake EnableGPIReservedWake Enable
TimeoutFlag
PeriodSelectOTGInterruptEnable
Out MailboxInterruptEnable
Reserved
SPI
InterruptEnableUARTInterruptEnable
Boost 3VOKLockEnableReserved
HSS
Wake EnableSleepEnableWDTEnable
0000 00000000 00000000 00000000 000F
SPI0000 0000Wake EnableHaltEnableResetStrobe
0000 00000000 00000000 0000
Table 15-1. Register Summary
WR/W
1: 0x0144SIEXmsg2: 0x01480x02n0
Device n Endpoint n Control
Data......DataReserved
IN/OUTSequenceIgnore EnableSelect
R/WR.WR/W
0x02n20x02n40x02n6
Device n Endpoint n AddressDevice n Endpoint n CountDevice n Endpoint n Status
Address......AddressReserved...CountReservedStallFlag
R/WR
0x02n80xC000
Device n Endpoint n Count Re-Result...sult
...ResultCPU Flags
Reserved......Reserved
R/WRR/W
0xC0020xC0040xC006
Bank
Hardware RevisionGPIO Control
Address......AddressRevision......RevisionWrite ProtectEnableHSSEnable
R/WR/W
0xC0080xC00A
CPU SpeedPower Control
Reserved....ReservedReserved
HPI ReservedWake Enable
R/W
0xC00C
Watchdog Timer
Reserved......Reserved
R/W
0xC00E
Interrupt Enable
Reserved
Host/Device 2Host/Device 10000 0000InterruptInterrupt EnableEnableTimer 1InterruptEnable
Timer 0Interrupt Enable
0001 0000
HSS Interrupt In MailboxEnableInterrupt
Enable
R/W
0xC098
OTG Control
ReservedD+
Pull-downEnable
R/WR/WR/WR/WRR/WR/W
0: 0xC010Timer n1: 0xC0120xC014
Count......Count...Address
1: 0xC018Extended Page n Map2: 0xC01A0xC01E0xC0200xC0220xC024
GPIO 0 Output DataGPIO 0 Input DataGPIO 0 DirectionGPIO 1 Output Data
Address......AddressGPIO15GPIO7GPIO15GPIO7GPIO15GPIO7GPIO31GPIO23
GPIO14GPIO6GPIO14GPIO6GPIO14GPIO6GPIO30GPIO22D-Pull-downEnable
GPIOInterruptEnable
VBUSReceivePull-up EnableDisableReserved
Charge PumpVBUS Dis-D+D-0000 0000
Enablecharge EnablePull-up EnablePull-up Enable
OTG Data Sta-ID
tusStatus
VBUS Valid
Flag
0000 0XXX
1111 11111111 11110000 00000000 0000
Breakpoint Address...GPIO13GPIO5GPIO13GPIO5GPIO13GPIO5GPIO29GPIO21
GPIO12GPIO4GPIO12GPIO4GPIO12GPIO4ReservedGPIO20
GPIO11GPIO3GPIO11GPIO3GPIO11GPIO3GPIO19
GPIO10GPIO2GPIO10GPIO2GPIO10GPIO2Reserved
GPIO9GPIO1GPIO9GPIO1GPIO9GPIO1
GPIO8GPIO0GPIO8GPIO0GPIO8GPIO0GPIO24
0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000
Document #: 38-08014 Rev. *EPage 93 of 98
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CY7C67200
Table 15-1. Register Summary (continued)
R/WRR/WR/W
AddressRegister0xC0260xC0280xC03C
GPIO 1 Input DataGPIO 1 DirectionUSB Diagnostic
Bit 15Bit 7GPIO31GPIO23GPIO31GPIO23Reserved...Reserved
R/W
0xC070
HSS Control
HSSEnable
Bit 14Bit 6GPIO30GPIO22GPIO30GPIO22
Bit 13Bit 5GPIO29GPIO21GPIO29GPIO21
Bit 12Bit 4ReservedGPIO20ReservedGPIO20
GPIO19
Reserved
Port 1A Diag-Reserved...nostic EnableFS Pull-upEnable
ReservedXOFFEnable
Force SelectCTSEnable
GPIO19
Reserved
GPIO24
Bit 11Bit 3
Bit 10Bit 2
Bit 9Bit 1
Bit 8Bit 0GPIO24
Default HighDefault Low0000 00000000 00000000 00000000 00000000 00000000 0000
Receive Inter-Done Interrupt0000 0000rupt EnableEnable
0000 00000000 00000001 01110000 00000000 1001xxxx xxxxxxxx xxxx0000 00000000 0000
Counter...
0000 00000000 00000000 00000000 0000
Counter...
0000 00000000 00000000 0000
Sequence
Select
SyncEnable
ISOEnable
Reserved
ArmEnable
0000 00000000 00000000 0000
Port Select
Reserved
OverflowFlag
NAKFlag
LengthReservedException Flag
SequenceStatus
UnderflowFlagTimeoutFlag
Count...ReservedErrorFlag
ACKFlag
0000 00000000 00000000 00000000 00000000 0000
Endpoint Select
0000 00000000 00000000 00000000 0000
Address
Port AD+ Status
Reserved
Port AD- StatusPort A Force D+/-State
Reserved
Reserved
LOASuspendEnable
ModeSelectReserved
ReservedPort ASOF/EOPEnableReserved
0000 0000xxxx 00000000 0000
Port 2A Diag-Reservednostic EnablePull-downEnable
LS Pull-upEnable
RTSCTS XOFFPolarity SelectPolarity Select
TransmitReadyHSS Baud...
Transmit Done Receive Done OneInterrupt FlagInterrupt FlagStop Bit
R/WR/WR/WR/WR/WR/WR/WR/W
0xC0720xC0740xC0760xC0780xC07A0xC07C0xC07E0xC0800xC0A00xC0820xC0A20xC0840xC0A40xC0860xC0A6
HSS Baud RateHSS Transmit GapHSS Data
HSS Receive AddressHSS Receive CounterHSS Transmit AddressHSS Transmit CounterHost n Control
Reserved...BaudReserved
Transmit Gap SelectReservedDataAddress......AddressReserved...CounterAddress.....AddressReserved...CounterReservedPreambleEnable
Host n AddressHost n CountHost n PID
Address......AddressReserved...CountReservedStallFlag
WRWR/W
0xC0860xC0A40xC0880xC0A80xC0880xC0A80xC08A0xC0AA
Host n EP StatusHost n Count ResultHost n Device AddressUSB n Control
ReservedPID SelectResult......ResultReserved......ReservedReservedPort A Resistors Enable
R/W
0xC08C
Host 1 Interrupt Enable
VBUSInterruptEnableReserved
PacketReceiveReceive Pack-ReceiveMode SelectOverflow Flaget Ready FlagReady Flag
R/WR/WR
ID
InterruptEnableSOF/EOPInterruptEnable
Port A Con-Reserved
nect Change InterruptEnable
SOF/EOPReservedTimeout Inter-rupt Enable
EP4InterruptEnable
EP3InterruptEnable
EP2InterruptEnable
SOF/EOPInterruptEnableEP1InterruptEnable
0000 0000
Port AReservedWake InterruptEnableID
InterruptEnableEP6InterruptEnableAddressID
InterruptFlag
ReservedReserved
Done InterruptEnableResetInterruptEnableEP0InterruptEnable
0000 0000
R/W0xC08CDevice 1 Interrupt Enable
VBUSInterruptEnableEP7InterruptEnable
0000 0000
EP5InterruptEnable
0000 0000
R/WR/W
0xC08E0xC0AE0xC090
Device n AddressHost 1 Status
Reserved......ReservedVBUS InterruptFlagReserved
SOF/EOPInterruptFlag
Port A Con-Reserved
nectChange
Interrupt Flag
Port ASE0Status
Reserved
Reserved
0000 00000000 0000xxxx xxxx
Port AReservedWake InterruptFlagDoneInterruptFlag
xxxx xxxx
Document #: 38-08014 Rev. *EPage 94 of 98
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CY7C67200
Table 15-1. Register Summary (continued)
R/WR/W
AddressRegister0xC090
Device 1 Status
Bit 15Bit 7VBUSInterruptFlagEP7InterruptFlag
R/WR
0xC0920xC0B20xC0920xC0B2
Host n SOF/EOP CountDevice n Frame Number
Reserved...CountSOF/EOPTimeoutFlag...Frame
RWRR/W
0xC0940xC0B40xC0940xC0B40xC0960xC0B60xC0AC
Host n SOF/EOP CounterDevice n SOF/EOP CountHost n Frame
Host 2 Interrupt Enable
Reserved...CounterReserved...CountReserved...FrameReserved
SOF/EOPInterruptEnable
Port AReservedWake InterruptEnable
Port A Con-Reserved
nect Change InterruptEnable
SOF/EOPWakeTimeout Inter-Interruptrupt EnableEnable
EP6InterruptEnable
EP5InterruptEnable
EP4InterruptEnable
EP3InterruptEnable
EP2InterruptEnable
SOF/EOPInterruptEnableEP1InterruptEnableSOF/EOPInterrupt Flag
Port AReservedWake InterruptFlag
Port A Con-Reserved
nect ChangeInterrupt Flag
SOF/EOPTimeoutInterruptEnable
Port ASE0StatusWakeInterruptFlag
Reserved
Reserved
Frame...
0000 00000000 00000000 0000
Count...Counter...
SOF/EOPTimeout
Interrupt Count
Reserved
Frame...
Bit 14Bit 6ID
InterruptFlagEP6InterruptFlag
Bit 13Bit 5Reserved
Bit 12Bit 4
Bit 11Bit 3
Bit 10Bit 2
Bit 9Bit 1SOF/EOPInterruptFlag
EP4InterruptFlag
EP3InterruptFlag
EP2InterruptFlag
EP1InterruptFlag
Bit 8Bit 0ResetInterruptFlagEP0InterruptFlag
Default HighDefault Lowxxxx xxxx
EP5InterruptFlagCount...
xxxx xxxx
0010 11101110 00000000 0000
0000 0000
Reserved
DoneInterruptEnableResetInterruptEnableEP0InterruptEnableReservedDoneInterruptFlagResetInterruptFlag
0000 0000
R/W0xC0ACDevice 2 Interrupt EnableReserved0000 0000
EP7InterruptEnable
R/W
0xC0B0
Host 2 Status
ReservedReserved
0000 0000
xxxx xxxxxxxx xxxx
R/W0xC0B0Device 2 StatusReserved
SOF/EOPInterruptFlag
xxxx xxxx
EP7EP6EP5EP4EP3EP2EP1
Interrupt FlagInterrupt FlagInterrupt FlagInterrupt FlagInterrupt FlagInterrupt FlagInterrupt Flag
R/WR/W
0xC0C60xC0C8
HPI MailboxSPI Configuration
Message......Message3WireEnable
PhaseSelect
SCKScale SelectPolarity SelectSSEnableByteMode
SS Delay SelectFullDuplex
SSManual
ReadEnable
TransmitReady
EP0xxxx xxxxInterrupt Flag
0000 00000000 0000
Reserved
1000 00000001 1111
ReceiveData Ready
0000 00011000 00000000 0000
MasterMasterActive EnableEnable
R/W
0xC0CA
SPI Control
SCKStrobeTransmitEmpty
R/W
0xC0CC
SPI Interrupt Enable
Reserved......Reserved
FIFOInitReceiveFull
Transmit Bit LengthReceive Bit Length
Receive Inter-TransmitruptInterrupt EnableEnable
Reserved
ReceiveTransmit
Interrupt FlagInterrupt Flag
TransferInterruptEnable
0000 0000
R0xC0CESPI StatusReserved...FIFO ErrorFlag
0000 0000
Transfer0000 0000Interrupt Flag
0000 0000
TransmitTransmit0000 0000Interrupt ClearInterrupt Clear
CRC Enable
CRC Clear
Receive CRCOne in CRC
Zero in CRC
Reserved...
0000 00000000 00001111 11111111 1111xxxx xxxxxxxx xxxx0000 00000000 0000
Count...
0000 00000000 0000
W0xC0D0SPI Interrupt ClearReserved......Reserved
R/WR/WR/WR/WR/W
0xC0D20xC0D40xC0D60xC0D80xC0DA
SPI CRC ControlSPI CRC ValueSPI Data Port tSPI Transmit AddressSPI Transmit Count
CRC Mode...ReservedCRC.....CRCReservedDataAddress......AddressReserved...Count
Document #: 38-08014 Rev. *EPage 95 of 98
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CY7C67200
Table 15-1. Register Summary (continued)
R/WR/WR/WR/W
AddressRegister0xC0DC0xC0DE0xC0E0
SPI Receive AddressSPI Receive CountUART Control
Bit 15Bit 7Address......AddressReserved...CountReserved......Reserved
R
0xC0E2
UART Status
Reserved......Reserved
R/WR
0xC0E4
UART DataHPI Status Port
ReservedDataVBUSFlagResume2Flag
IDFlagResume1Flag
ReservedSIE2msg
SOF/EOP2FlagSIE1msg
ReservedDone2Flag
SOF/EOP1FlagDone1Flag
Reset2FlagReset1Flag
Mailbox InFlagMailbox OutFlag
ReceiveFull
Transmit Full
ScaleSelect
BaudSelect
UARTEnable
Count...
Bit 14Bit 6
Bit 13Bit 5
Bit 12Bit 4
Bit 11Bit 3
Bit 10Bit 2
Bit 9Bit 1
Bit 8Bit 0
Default HighDefault Low0000 00000000 00000000 00000000 00000000 00000000 01110000 00000000 00000000 00000000 0000
Document #: 38-08014 Rev. *EPage 96 of 98
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CY7C67200
16.0
Ordering Information
Ordering Code
Package Type
Temperature Range
Table 16-1. Ordering Information
CY7C67200-48BAICY3663
48 FBGADevelopment Kit
–40 to 85°C
17.0 Package Diagrams48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A51-85096-*EPurchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the PhilipsI2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specificationas defined by Philips. EZ-OTG is a trademark of Cypress Semiconductor. All product and company names mentioned in thisdocument are trademarks of their respective holders.
Document #: 38-08014 Rev. *EPage 97 of 98
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorizeits products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of CypressSemiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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CY7C67200
Document History Page
Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral ControllerDocument Number: 38-08014REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
***A*B
111872116988124954
03/22/0208/23/0204/10/03
MULMULMUL
New Data SheetPreliminary Data Sheet
Added Memory Map Section and Ordering Information SectionMoved Functional Register Map Tables into Register sectionGeneral Clean-up
Changed from “Preliminary“ to “Preliminary Confidential“
Added Interface Description Section and Power Savings and Reset SectionAdded Char DataGeneral Clean-up
Removed DRAM, MDMA, and EPP Added “Programmable” to the title pageCorrected font to enable correct symbol displayFinal Data Sheet
Changed Memory Map SectionAdded USB OTG LogoGeneral Clean-up
*C12621105/23/03MUL
*D*E
127334129394
05/29/0310/07/03
KKVMUL
Document #: 38-08014 Rev. *EPage 98 of 98
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