MPC850DE

Topic

Page

Part I, “Overview”Part II, “Features”

Part III, “Electrical and Thermal Characteristics”Part IV, “Thermal Characteristics”Part V, “Power Considerations”Part VI, “Bus Signal Timing”

Part VII, “IEEE 1149.1 Electrical Specifications”Part VIII, “CPM Electrical Characteristics”

Part IX, “Mechanical Data and Ordering Information”Part X, “Document Revision History”1371037396167

Part I Overview

The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combinationthat can be used in a variety of controller applications, excelling particularly incommunications and networking products. The MPC850, which includes support forEthernet, is specifically designed for cost-sensitive, remote-access, and telecommunicationsapplications. It is provides functions similar to the MPC860, with system enhancements suchas universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM.

In addition to a high-performance embedded MPC8xx core, the MPC850 integrates systemfunctions, such as a versatile memory controller and a communications processor module(CPM) that incorporates a specialized, independent RISC communications processor(referred to as the CP). This separate processor off-loads peripheral tasks from the embeddedMPC8xx core.

The CPM of the MPC850 supports up to seven serial channels, as follows:

•

One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SAR), HDLC and a number of other protocols, along with a transparent mode of operation.

••••

One USB channel

Two serial management controllers (SMCs)One I2C port

One serial peripheral interface (SPI).

Table 1 shows the functionality supported by the members of the MPC850 family.

Table 1. MPC850 Functionality Matrix

Part

Number of SCCs Supported

Ethernet SupportYesYesYes

ATM Support

--Yes

USB Support

YesYesYes

Number of

Multi-channel

PCMCIA Slots

HDLC Support

Supported

--Yes

111

MPC850 1MPC850DEMPC850SAR

22

Additional documentation may be provided for parts listed in Table 1.

2MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Part II Features

Figure 1 is a block diagram of the MPC850, showing its major components and the relationships amongthose components:

2-KbyteI-CacheEmbeddedMPC8xxCoreInstructionBusInstructionMMU1-KbyteD-CacheLoad/Store BusDataMMUSystem Interface UnitMemory ControllerUnified BusBus Interface UnitSystem FunctionsReal-Time ClockPCMCIA InterfaceBaud RateGeneratorsParallel I/O Ports —UTOPIA(850SAR)FourTimersInterruptControllerDual-PortRAM20 VirtualSerial DMAChannelsand2 VirtualIDMAChannelsPeripheral BusCommunicationsProcessorModule32-Bit RISC CommunicationsProcessor (CP) and Program ROMTimerSCC2TDMaSCC3SMC1SMC2USBSPII2CTime Slot AssignerNon-Multiplexed Serial InterfaceFigure 1. MPC850 Microprocessor Block Diagram

The following list summarizes the main features of the MPC850:

•

Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)

—Performs branch folding and branch prediction with conditional prefetch, but without

conditional execution

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 3

—2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)

–Caches are two-way, set-associative –Physically addressed

–Cache blocks can be updated with a 4-word line burst–Least-recently used (LRU) replacement algorithm–Lockable one-line granularity

—Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and

fully-associative instruction and data TLBs—MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and

8 Mbytes; 16 virtual address spaces and eight protection groups••

Advanced on-chip emulation debug mode

Data bus dynamic bus sizing for 8, 16, and 32-bit buses

—Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian

memory systems—Twenty-six external address lines••

Completely static design (0–80 MHz operation)System integration unit (SIU)—Hardware bus monitor—Spurious interrupt monitor—Software watchdog—Periodic interrupt timer—Low-power stop mode—Clock synthesizer

—Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture —Reset controller

—IEEE 1149.1 test access port (JTAG)•

Memory controller (eight banks)

—Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM

(SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), flash EPROM, etc.—Memory controller programmable to support most size and speed memory interfaces—Boot chip-select available at reset (options for 8, 16, or 32-bit memory)—Variable block sizes, 32 Kbytes to 256 Mbytes—Selectable write protection

—On-chip bus arbiter supports one external bus master—Special features for burst mode support•

General-purpose timers

—Four 16-bit timers or two 32-bit timers —Gate mode can enable/disable counting

4MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

—Interrupt can be masked on reference match and event capture•

Interrupts

—Eight external interrupt request (IRQ) lines—Twelve port pins with interrupt capability—Fifteen internal interrupt sources

—Programmable priority among SCCs and USB—Programmable highest-priority request•

Single socket PCMCIA-ATA interface

—Master (socket) interface, release 2.1 compliant—Single PCMCIA socket

—Supports eight memory or I/O windows•

Communications processor module (CPM)

—32-bit, Harvard architecture, scalar RISC communications processor (CP)

—Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission

after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor)—Supports continuous mode transmission and reception on all serial channels —Up to 8 Kbytes of dual-port RAM

—Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four

USB endpoints—Three parallel I/O registers with open-drain capability•

Four independent baud-rate generators (BRGs)—Can be connected to any SCC, SMC, or USB—Allow changes during operation —Autobaud support option•

Two SCCs (serial communications controllers)

—Ethernet/IEEE 802.3, supporting full 10-Mbps operation—HDLC/SDLC™ (all channels supported at 2 Mbps)

—HDLC bus (implements an HDLC-based local area network (LAN))—Asynchronous HDLC to support PPP (point-to-point protocol)—AppleTalk®

—Universal asynchronous receiver transmitter (UART)—Synchronous UART—Serial infrared (IrDA)

—Totally transparent (bit streams)

—Totally transparent (frame based with optional cyclic redundancy check (CRC))•

QUICC multichannel controller (QMC) microcode features—Up to independent communication channels on a single SCC—Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots

MOTOROLA

MPC850 (Rev. A/B/C) Hardware Specifications

5

—Supports either transparent or HDLC protocols for each channel—Independent TxBDs/Rx and event/interrupt reporting for each channel••

One universal serial bus controller (USB)

—Supports host controller and slave modes at 1.5 Mbps and 12 MbpsTwo serial management controllers (SMCs)—UART—Transparent

—General circuit interface (GCI) controller

—Can be connected to the time-division-multiplexed (TDM) channel•

One serial peripheral interface (SPI)—Supports master and slave modes

—Supports multimaster operation on the same bus•

One I2C® (interprocessor-integrated circuit) port—Supports master and slave modes—Supports multimaster environment•

Time slot assigner

—Allows SCCs and SMCs to run in multiplexed operation

—Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined—1- or 8-bit resolution

—Allows independent transmit and receive routing, frame syncs, clocking —Allows dynamic changes

—Can be internally connected to four serial channels (two SCCs and two SMCs)•

Low-power support

—Full high: all units fully powered at high clock frequency—Full low: all units fully powered at low clock frequency

—Doze: core functional units disabled except time base, decrementer, PLL, memory controller,

real-time clock, and CPM in low-power standby—Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for

fast wake-up—Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt

timer—Low-power stop: to provide lower power dissipation

—Separate power supply input to operate internal logic at 2.2 V when operating at or below

25 MHz—Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V

internal) operation•

Debug interface

—Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data

6MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

—The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints —Each watchpoint can generate a breakpoint internally•

3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins.

Part III Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850.Table 2 provides the maximum ratings.

Table 2. Maximum Ratings

(GND = 0V)

RatingSupply voltageSymbolVDDHVDDLKAPWRVDDSYN-0.3 to 4.0-0.3 to 4.0-0.3 to 4.0-0.3 to 4.0ValueUnitVVVVV˚C˚CInput voltage 1Junction temperature 2Storage temperature range1VinTjTstgGND-0.3 to VDDH + 2.5 V0 to 95 (standard)-40 to 95 (extended)-55 to +150Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device.

CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not be applied to its inputs).

2The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of the device.

This device contains circuitry protecting against damage due to high-static voltage or electrical fields;however, it is advised that normal precautions be taken to avoid application of any voltages higher thanmaximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unusedinputs are tied to an appropriate logic voltage level (for example, either GND or VCC). Table 3 provides thepackage thermal characteristics for the MPC850.

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 7

Part IV Thermal Characteristics

Table 3 shows the thermal characteristics for the MPC850.

Table 3. Thermal Characteristics

CharacteristicThermal resistance for BGA 1Symbol θJA θJA θJAThermal Resistance for BGA (junction-to-case)1Value40 2 31 324 48Unit°C/W°C/W°C/W°C/W θJC For more information on the design of thermal vias on multilayer boards and BGA layout considerations in general, refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Motorola sales office.2Assumes natural convection and a single layer board (no thermal vias).3Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board temperature rise of 20°C above ambient.4Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board temperature rise of 13°C above ambient.TJ = TA + (PD •θJA)PD = (VDD • IDD) + PI/OPI/O is the power dissipation on pinswhere:Table 4 provides power dissipation information.Table 4. Power Dissipation (PD)CharacteristicPower Dissipation All Revisions(1:1) Mode12Frequency (MHz)334050Typical 1TBDTBDTBDMaximum 2515590725UnitmWmWmWTypical power dissipation is measured at 3.3VMaximum power dissipation is measured at 3.65 VTable 5 provides the DC electrical characteristics for the MPC850. Table 5. DC Electrical Specifications CharacteristicOperating voltage at 40 MHz or lessOperating voltage at 40 MHz or higherInput high voltage (address bus, data bus, EXTAL, EXTCLK, and all bus control/status signals)Input high voltage (all general purpose I/O and peripheral pins)SymbolVDDH, VDDL, KAPWR, VDDSYNVDDH, VDDL, KAPWR, VDDSYNVIHVIHMin3.03.1352.02.0Max3.63.4653.65.5UnitVVVV8MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Table 5. DC Electrical Specifications (continued)

CharacteristicInput low voltageEXTAL, EXTCLK input high voltageInput leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins)Input leakage current, Vin = 3.6V (Except TMS, TRST, DSCK and DSDI pins)Input leakage current, Vin = 0V (Except TMS, TRST, DSCK and DSDI pins)Input capacitanceOutput high voltage, IOH = -2.0 mA, VDDH = 3.0Vexcept XTAL, XFC, and open-drain pinsOutput low voltageIOL = 2.0 mA CLKOUTIOL = 3.2 mA 1IOL = 5.3 mA 2IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2IOL = 8.9 mA TS, TA, TEA, BI, BB, HRESET, SRESET1SymbolVILVIHCIinIInIInCinVOHVOLMinGND0.7*(VCC)————2.4—Max0.8VCC+0.3100101020—0.5UnitVVµAµAµApFVVA[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1], IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2,

PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/TOUT1/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2, PA[4]/CLK4/TOUT2/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3, PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3, PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1, PB[18]/RTS2/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6, PC[13]/L1ST7/RTS3, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2, PC[8]/CD2/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA, PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3]

BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR, WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1, OP2/MODCK1/STS, OP3/MODCK2/DSDO2

Part V Power Considerations

The average chip-junction temperature, TJ, in °C can be obtained from the equation:

TJ = TA + (PD • θJA)where

TA = Ambient temperature, °C

θJA = Package thermal resistance, junction to ambient, °C/WPD = PINT + PI/O

PINT = IDD x VDD, watts—chip internal power

PI/O = Power dissipation on input and output pins—user determined

MOTOROLA

MPC850 (Rev. A/B/C) Hardware Specifications

9

(1)

Layout Practices

For most applications PI/O < 0.3 • PINT and can be neglected. If PI/O is neglected, an approximate relationshipbetween PD and TJ is:

PD = K ÷ (TJ+ 273°C)

(2)

2

Solving equations (1) and (2) for K gives:

K = PD • (TA + 273°C) + θJA • PD

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuringPD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solvingequations (1) and (2) iteratively for any value of TA.

5.1Layout Practices

Each VCC pin on the MPC850 should be provided with a low-impedance path to the board’s supply. EachGND pin should likewise be provided with a low-impedance path to ground. The power supply pins drivedistinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads andassociated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inchper capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection lengthshould be minimized in order to minimize undershoot and reflections caused by these fast output switchingtimes. This recommendation particularly applies to the address and data busses. Maximum PC trace lengthsof six inches are recommended. Capacitance calculations should consider all device loads as well asparasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomesespecially critical in systems with higher capacitive loads because these loads create higher transientcurrents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.Special care should be taken to minimize the noise levels on the PLL supply pins.

Part VI Bus Signal Timing

Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timinginformation for other bus speeds can be interpolated by equation using the MPC850 ElectricalSpecifications Spreadsheet found at http://www.mot.com/netcomm.

The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated inhalf-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus). The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10 pF.Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.

10MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Table 6. Bus Operation Timing 1

50 MHz

NumB1B1a

Characteristic

Min

CLKOUT period

EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF <= 2)

EXTCLK to CLKOUT phase skew (EXTCLK > 10 MHz and MF < 10)

20-0.90

Max—0.90

Min30.30-0.90

Max—0.90

Min25-0.90

Max—0.90

——

66 MHz

80 MHz

FFACT

Cap Load (default 50 pF)

—50.00

Unitnsns

B1b-2.302.30-2.302.30-2.302.30—50.00ns

B1cB1dB1eB1fB1gB1hB2B3B4B5B7

CLKOUT phase jitter (EXTCLK > -0.6015 MHz and MF <= 2) 2CLKOUT phase jitter 2CLKOUT frequency jitter (MF < 10) 2

CLKOUT frequency jitter (10 < MF < 500) 2

CLKOUT frequency jitter (MF > 500) 2

Frequency jitter on EXTCLK 3CLKOUT pulse width lowCLKOUT width highCLKOUT rise timeCLKOUT fall time

CLKOUT to A[6–31],

RD/WR, BURST, D[0–31], DP[0–3] invalid

CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3], BDIP, PTR invalidCLKOUT to BR, BG, FRZ, VFLS[0–1], VF[0–2] IWP[0–2], LWP[0–1], STS invalid 4CLKOUT to A[6–31],

RD/WR, BURST, D[0–31], DP[0–3] valid

CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3] BDIP, PTR validCLKOUT to BR, BG, VFLS[0–1], VF[0–2], IWP[0–2], FRZ, LWP[0–1], STS valid 4

CLKOUT to A[6–31] RD/WR, BURST, D[0–31], DP[0–3], TSIZ[0–1], REG, RSV, AT[0–3], PTR high-Z-2.00————8.008.00——5.00

0.602.000.502.003.000.50——4.004.00—

-0.60-2.00————12.1212.12——7.58

0.602.000.502.003.000.50——4.004.00—

-0.60-2.00————10.0010.00——6.25

0.602.000.502.003.000.50——4.004.00—

——————————0.250

50.0050.0050.0050.0050.0050.0050.0050.0050.0050.0050.00

nsns%%%%nsnsnsnsns

B7aB7b

5.005.00

——

7.587.58

——

6.256.25

——

0.2500.250

50.0050.00

nsns

B85.0011.757.5814.336.2513.000.25050.00ns

B8aB8b

5.005.00

11.7511.74

7.587.58

14.3314.33

6.256.25

13.0013.00

0.2500.250

50.0050.00

nsns

B95.0011.757.5814.336.2513.000.25050.00ns

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 11

Layout Practices

Table 6. Bus Operation Timing 1 (continued)

50 MHz

NumB11

Characteristic

Min

CLKOUT to TS, BB assertion5.002.50

Max11.009.25

Min7.582.50

Max13.5.25

Min6.252.50

Max12.259.25

0.250—

66 MHz

80 MHz

FFACT

Cap Load (default 50 pF)50.0050.00

Unitnsns

B11aCLKOUT to TA, BI assertion, (When driven by the memory controller or PCMCIA interface)B12

CLKOUT to TS, BB negation5.002.50

11.7511.00

7.582.50

14.3311.00

6.252.50

13.0011.00

0.250—

50.0050.00

nsns

B12aCLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface)B13

CLKOUT to TS, BB high-Z5.0019.0015.00

7.582.50

21.5815.00

6.252.50

20.2515.00

0.250—

50.0050.00

nsns

B13aCLKOUT to TA, BI high-Z, (when 2.50

driven by the memory controller or PCMCIA interface)B14B15B16

CLKOUT to TEA assertionCLKOUT to TEA high-ZTA, BI valid to CLKOUT(setup time) 5

2.502.509.7510.008.50

10.0015.00——————

2.502.509.7510.008.501.002.006.00

10.0015.00——————

2.502.509.7510.008.501.002.006.00

10.0015.00——————

————————

50.0050.0050.0050.0050.0050.0050.0050.00

nsnsnsnsnsnsnsns

B16aTEA, KR, RETRY, valid to CLKOUT (setup time) 5B16bBB, BG, BR valid to CLKOUT (setup time) 6B17

CLKOUT to TA, TEA, BI, BB, BG, 1.00BR valid (Hold time).5

2.006.00

B17aCLKOUT to KR, RETRY, except TEA valid (hold time)B18

D[0–31], DP[0–3] valid to CLKOUT rising edge (setup time) 7

B19B20

CLKOUT rising edge to D[0–31], 1.00DP[0–3] valid (hold time) 7D[0–31], DP[0–3] valid to CLKOUT falling edge (setup time) 8

4.00

——

1.004.00

——

1.004.00

——

——

50.0050.00

nsns

B21B22

CLKOUT falling edge to D[0–31], 2.00DP[0–3] valid (hold time) 8CLKOUT rising edge to CS asserted GPCM ACS = 00

5.00—

—11.758.00

2.007.58—

—14.338.00

2.006.25—

—13.008.00

—0.250—

—50.0050.00

—nsns

B22aCLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0,1

B22bCLKOUT falling edge to CS 5.00

asserted GPCM ACS = 11, TRLX = 0, EBDF = 0

11.757.5814.336.2513.000.25050.00ns

12MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Table 6. Bus Operation Timing 1 (continued)

50 MHz

Num

Characteristic

Min

B22cCLKOUT falling edge to CS 7.00

asserted GPCM ACS = 11, TRLX = 0, EBDF = 1B23

CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0

A[6–31] to CS asserted GPCM ACS = 10, TRLX = 0.

2.00

Max

Min

Max

Min9.00

Max16.00

0.375

14.0011.0018.00

66 MHz

80 MHz

FFACT

Cap Load (default 50 pF)50.00

Unitns

8.002.008.002.008.00—50.00ns

B243.008.00—2.0023.0028.00—

——9.009.00——9.00

6.0013.00—2.0036.0043.00—

——9.009.00——9.00

4.0011.00—2.0029.0036.00—

——9.009.00——9.00

0.2500.500——1.2501.500—

50.0050.0050.0050.0050.0050.0050.00

nsnsnsnsnsnsns

B24aA[6–31] to CS asserted GPCM ACS = 11, TRLX = 0B25B26B27

CLKOUT rising edge to OE, WE[0–3] assertedCLKOUT rising edge to OE negated

A[6–31] to CS asserted GPCM ACS = 10, TRLX = 1

B27aA[6–31] to CS asserted GPCM ACS = 11, TRLX = 1B28

CLKOUT rising edge to WE[0–3] negated GPCM write access CSNT = 0

B28aCLKOUT falling edge to WE[0–3] 5.00

negated GPCM write access TRLX = 0,1 CSNT = 1, EBDF = 0B28bCLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0

—

12.008.0014.006.0013.000.25050.00ns

12.00—14.00—13.000.25050.00ns

B28cCLKOUT falling edge to WE[0–3] 7.00

negated GPCM write access TRLX = 0,1 CSNT = 1 write access TRLX = 0, CSNT = 1, EBDF = 1B28dCLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1B29

WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, CSNT = 0

—

14.0011.0018.009.0016.000.37550.00ns

14.00—18.00—16.000.37550.00ns

3.00—6.00—4.00—0.25050.00ns

B29aWE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 0 CSNT = 1, EBDF = 0

8.00—13.00—11.00—0.50050.00ns

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 13

Layout Practices

Table 6. Bus Operation Timing 1 (continued)

50 MHz

Num

Characteristic

Min

B29bCS negated to D[0–31], DP[0–3], 3.00

high-Z GPCM write access, ACS = 00, TRLX = 0 & CSNT = 0B29c CS negated to D[0–31], DP[0–3] 8.00

high-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0B29dWE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0

28.00

Max—

Min6.00

Max—

Min4.00

Max—

0.250

66 MHz

80 MHz

FFACT

Cap Load (default 50 pF)50.00

Unitns

—13.00—11.00—0.50050.00ns

—43.00—36.00—1.50050.00ns

B29eCS negated to D[0–31], DP[0–3] 28.00

high-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0B29f

WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, EBDF = 1

5.00

—43.00—36.00—1.50050.00ns

—9.00—7.00—0.37550.00ns

B29gCS negated to D[0–31], DP[0–3] 5.00

high-Z GPCM write access TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1B29hWE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, EBDF = 1B29i

25.00

—9.00—7.00—0.37550.00ns

—39.00—31.00—1.37550.00ns

CS negated to D[0–31], DP[0–3] 25.00high-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1

CS, WE[0–3] negated to A[6–31] 3.00invalid

GPCM write access 9

—39.00—31.00—1.37550.00ns

B30—6.00—4.00—0.25050.00ns

B30aWE[0–3] negated to A[6–31] 8.00

invalid

GPCM write access, TRLX = 0, CSNT = 1, CS negated to A[6–31] invalid GPCM write access TRLX = 0, CSNT =1, ACS = 10 or ACS = 11, EBDF = 0

—13.00—11.00—0.50050.00ns

14MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Table 6. Bus Operation Timing 1 (continued)

50 MHz

Num

Characteristic

Min

28.00B30bWE[0–3] negated to A[6–31] invalid

GPCM write access, TRLX = 1, CSNT = 1. CS negated to A[6–31] Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0B30cWE[0–3] negated to A[6–31] 5.00

invalid

GPCM write access, TRLX = 0, CSNT = 1. CS negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 B30dWE[0–3] negated to A[6–31] 25.00

invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A[6–31] invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1B31

CLKOUT falling edge to CS valid 1.50- as requested by control bit CST4 in the corresponding word in the UPM

Max—

Min43.00

Max—

Min36.00

Max—

1.500

66 MHz

80 MHz

FFACT

Cap Load (default 50 pF)50.00

Unitns

—8.00—6.00—0.37550.00ns

—39.00—31.00—1.37550.00ns

6.001.506.001.506.00—50.00ns

B31aCLKOUT falling edge to CS valid 5.00

- as requested by control bit CST1 in the corresponding word in the UPMB31bCLKOUT rising edge to CS valid 1.50

- as requested by control bit CST2 in the corresponding word in the UPMB31cCLKOUT rising edge to CS valid 5.00

- as requested by control bit CST3 in the corresponding word in the UPMB31dCLKOUT falling edge to CS valid 9.00

- as requested by control bit CST1 in the corresponding word in the UPM EBDF = 1B32

CLKOUT falling edge to BS valid 1.50- as requested by control bit BST4 in the corresponding word in the UPM

12.008.0014.006.0013.000.25050.00ns

8.001.508.001.508.00—50.00ns

12.008.0014.006.0013.000.25050.00ns

14.0013.0018.0011.0016.000.37550.00ns

6.001.506.001.506.00—50.00ns

B32aCLKOUT falling edge to BS valid 5.00

- as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0

12.008.0014.006.0013.000.25050.00ns

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 15

Layout Practices

Table 6. Bus Operation Timing 1 (continued)

50 MHz

Num

Characteristic

Min

B32bCLKOUT rising edge to BS valid 1.50

- as requested by control bit BST2 in the corresponding word in the UPMB32cCLKOUT rising edge to BS valid 5.00

- as requested by control bit BST3 in the corresponding word in the UPMB32dCLKOUT falling edge to BS valid 9.00

- as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1B33

1.50CLKOUT falling edge to GPL

valid - as requested by control bit GxT4 in the corresponding word in the UPM

Max8.00

Min1.50

Max8.00

Min1.50

Max8.00

—

66 MHz

80 MHz

FFACT

Cap Load (default 50 pF)50.00

Unitns

12.008.0014.006.0013.000.25050.00ns

14.0013.0018.0011.0016.000.37550.00ns

6.001.506.001.506.00—50.00ns

5.00B33aCLKOUT rising edge to GPL

valid - as requested by control bit GxT3 in the corresponding word in the UPMB34 A[6–31] and D[0–31] to CS valid 3.00

- as requested by control bit CST4 in the corresponding word in the UPMB34aA[6–31] and D[0–31] to CS valid 8.00

- as requested by control bit CST1 in the corresponding word in the UPMB34bA[6–31] and D[0–31] to CS valid 13.00

- as requested by CST2 in the corresponding word in UPMB35

A[6–31] to CS valid - as 3.00requested by control bit BST4 in the corresponding word in UPM

12.008.0014.006.0013.000.25050.00ns

—6.00—4.00—0.25050.00ns

—13.00—11.00—0.50050.00ns

—21.00—17.00—0.75050.00ns

—6.00—4.00—0.25050.00ns

B35aA[6–31] and D[0–31] to BS valid 8.00

- as requested by BST1 in the corresponding word in the UPM B35bA[6–31] and D[0–31] to BS valid 13.00

- as requested by control bit BST2 in the corresponding word in the UPMB36

3.00A[6–31] and D[0–31] to GPL

valid - as requested by control bit GxT4 in the corresponding word in the UPM

—13.00—11.00—0.50050.00ns

—21.00—17.00—0.75050.00ns

—6.00—4.00—0.25050.00ns

16MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Table 6. Bus Operation Timing 1 (continued)

50 MHzNumB37B38B39B40CharacteristicMinUPWAIT valid to CLKOUT falling 6.00edge 10CLKOUT falling edge to UPWAIT 1.00valid 10 1166 MHzMin6.001.007.007.00Max————80 MHzFFACTMin6.001.007.007.00Max————————Max————Cap Load (default 50 pF)50.0050.0050.0050.00UnitnsnsnsnsAS valid to CLKOUT rising edge 7.007.00A[6–31], TSIZ[0–1], RD/WR, BURST, valid to CLKOUT rising edge.B41B42B431TS valid to CLKOUT rising edge 7.00(setup time)CLKOUT rising edge to TS valid (hold time)AS negation to memory controller signals negation2.00———TBD7.002.00———TBD7.002.00TBD——————50.0050.0050.00nsnsnsThe minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC

parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part. The following equations should be used in these calculations.

For a frequency F, the following equations should be applied to each one of the above parameters: For minima:

FFACTOR x 1000(D50 - 20 x FFACTOR)D =+

FFor maxima:

FFACTOR x 1000(D50 -20 x FFACTOR) 1ns(CAP LOAD - 50) / 10

++D =

F

where:

D is the parameter value to the frequency required in nsF is the operation frequency in MHz

D50 is the parameter value defined for 50 MHz

CAP LOAD is the capacitance load on the signal in question.

FFACTOR is the one defined for each of the parameters in the table.

2Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value. 3If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the maximum allowed jitter on EXTAL can be up to 2%.

4The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for BG output is relevant when the MPC850 is selected to work with internal bus arbiter.

5The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and not when the memory controller or the PCMCIA interface drives them).

6The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter.7The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 17

Layout Practices

8

The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.9The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.10The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals.11The AS signal is considered asynchronous to CLKOUT.

Figure 2 is the control timing diagram.

CLKOUT

2.0 V0.8 VAB0.8 V2.0 VOutputs

2.0 V0.8 V2.0 V0.8 VABOutputs

2.0 V0.8 VDC2.0 V0.8 VInputs

2.0 V0.8 V2.0 V0.8 VDCInputs

2.0 V0.8 V2.0 V0.8 VABCDMaximum output delay specificationMinimum output hold time

Minimum input setup time specificationMinimum input hold time specification

Figure 2. Control Timing

18MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 3 provides the timing for the external clock.

CLKOUT

B1B1B4B3B2B5Figure 3. External Clock Timing

Figure 4 provides the timing for the synchronous output signals.

CLKOUT

B8B7OutputSignals

B8aB7aOutputSignals

B8bB7bOutputSignals

B9B9Figure 4. Synchronous Output Signals Timing

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 19

Layout Practices

Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13B11TS, BB

B13aB11aTA, BI

B14B15TEA

B12aB12Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing

Figure 6 provides the timing for the synchronous input signals.

CLKOUTB16B17TA, BIB16aB17aTEA, KR,RETRYB16bB17BB, BG, BRFigure 6. Synchronous Input Signals Timing

20MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 7 provides normal case timing for input data.

CLKOUT

B16B17TA

B18B19D[0:31],DP[0:3]

Figure 7. Input Data Timing in Normal Case

Figure 8 provides the timing for the input data controlled by the UPM in the memory controller.

CLKOUT

TA

B20B21D[0:31],DP[0:3]

Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 21

Layout Practices

Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors.

CLKOUT

B11TSB8A[6:31]

B22CSxB25OEB28WE[0:3]B18D[0:31],DP[0:3]

B19B26B23B12Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00)

22MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

CLKOUT

B11TSB8A[6:31]

B22aB12B23CSxB24OEB18D[0:31],DP[0:3]

B19B25B26Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)

CLKOUT

B11TS

B8A[6:31]

B22cCSx

B24aOE

B18D[0:31],DP[0:3]

B19B25B26B23B22bB12Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 23

Layout Practices

CLKOUT

B11TS

B8A[6:31]

B22aCSx

B27OE

B27aB22bB22cD[0:31],DP[0:3]

B18B19B26B23B12Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)

24MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCMfactors.

CLKOUT

B11TS

B8A[6:31]

B22CSx

B25WE[0:3]

B26OE

B8D[0:31],DP[0:3]

B9B29B29aB28B23B30B12Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 25

Layout Practices

CLKOUT

B11TS

B8A[6:31]

B22CSx

B25WE[0:3]

B26OE

B8D[0:31],DP[0:3]

B28aB28cB9B29aB29fB29cB29gB28bB28dB23B30aB30cB12Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)

26MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

CLKOUT

B11TS

B8A[6:31]

B22CSx

B25WE[0:3]

B26OE

B8D[0:31],DP[0:3]

B28aB28cB29dB29B9B29eB29iB28bB28dB23B30bB30dB12Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)

Figure 16 provides the timing for the external bus controlled by the UPM.

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 27

Layout Practices

CLKOUT

B8A[6:31]

B31aB31dB31CSx

B34B34aB34bB32aB32dB32BS_A[0:3],BS_B[0:3]

B35B36B35aB35bB33GPL_A[0–5],GPL_B[0–5]

B33aB32bB32cB31bB31cFigure 16. External Bus Timing (UPM Controlled Signals)

Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

CLKOUTB37UPWAITB38CSxBS_A[0:3],BS_B[0:3]GPL_A[0–5],GPL_B[0–5]

Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

28MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.

CLKOUTB37UPWAITB38CSxBS_A[0:3],BS_B[0:3]GPL_A[0–5],GPL_B[0–5]Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles TimingFigure 19 provides the timing for the synchronous external master access controlled by the GPCM.

CLKOUT

B41TS

B40A[6:31],TSIZ[0:1],R/W, BURST

B22CSx

B42Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 29

Layout Practices

Figure 20 provides the timing for the asynchronous external master memory access controlled by theGPCM.

CLKOUT

B39AS

B40A[6:31],TSIZ[0:1],R/W

B22CSx

Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 21 provides the timing for the asynchronous external master control signals negation.

AS

B43CSx, WE[0:3],OE, GPLx,BS[0:3]

Figure 21. Asynchronous External Master—Control Signals Negation Timing

Table 7 provides interrupt timing for the MPC850.

Table 7. Interrupt Timing

NumI39I40I41I42I431Characteristic 1IRQx valid to CLKOUT rising edge (set up time)IRQx hold time after CLKOUT.IRQx pulse width lowIRQx pulse width highIRQx edge-to-edge time50 MHzMin6.002.003.003.0080.00Max—————66MHzMin6.002.003.003.00121.0Max—————80 MHzUnitMin6.002.003.003.00100.0Max—————nsnsnsnsnsThe timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT.

The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the MPC850 is able to support

30MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 22 provides the interrupt detection timing for the external level-sensitive lines.

CLKOUT

I39I40IRQx

Figure 22. Interrupt Detection Timing for External Level Sensitive Lines

Figure 23 provides the interrupt detection timing for the external edge-sensitive lines.

CLKOUT

I39I41IRQx

I43I43I42Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines

Table 8 shows the PCMCIA timing for the MPC850.

Table 8. PCMCIA Timing

50MHz

Num

Characteristic

Min

P44P45P46P47P48P49P50P51P52

A[6–31], REG valid to PCMCIA strobe asserted. 1

A[6–31], REG valid to ALE negation.1CLKOUT to REG validCLKOUT to REG Invalid.CLKOUT to CE1, CE2 asserted. CLKOUT to CE1, CE2 negated. CLKOUT to PCOE, IORD, PCWE, IOWR assert time.

CLKOUT to PCOE, IORD, PCWE, IOWR negate time.

CLKOUT to ALE assert time

13.0018.005.006.005.005.00—2.005.00

Max——13.00—13.0013.0011.0011.0013.00

Min21.0028.008.009.008.008.00—2.008.00

Max——16.00—16.0016.0011.0011.0016.00

Min17.0023.006.007.006.006.00—2.006.00

Max——14.00—14.0014.0011.0011.0014.00

0.7501.0000.2500.2500.2500.250——0.250

nsnsnsnsnsnsnsns

66MHz

80 MHz

FFACTORUnit

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 31

Layout Practices

Table 8. PCMCIA Timing (continued)

50MHzNumP53P54P55P56166MHzMin—6.008.002.00Max16.00———80 MHzFFACTORUnitMin—4.008.002.00Max14.00———0.2500.250——nsnsnsnsCharacteristicMinCLKOUT to ALE negate timePCWE, IOWR negated to D[0–31] invalid.1WAIT_B valid to CLKOUT rising edge.1CLKOUT rising edge to WAIT_B invalid.1—3.008.002.00Max13.00———PSST = 1. Otherwise add PSST times cycle time.PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.

Figure 24 provides the PCMCIA access cycle timing for the external bus read.

CLKOUT

TS

P44A[6:31]

P46REG

P48CE1/CE2

P50PCOE, IORD

P52ALE

B18D[0:31]

B19P53P52P51P49P45P47Figure 24. PCMCIA Access Cycles Timing External Bus Read

32MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 25 provides the PCMCIA access cycle timing for the external bus write.

CLKOUT

TS

P44A[6:31]

P46REG

P48CE1/CE2

P50PCOE, IOWR

P52ALE

B8D[0:31]

B9P53P52P51P54P49P45P47Figure 25. PCMCIA Access Cycles Timing External Bus Write

Figure 26 provides the PCMCIA WAIT signals detection timing.

CLKOUT

P55P56WAIT_BFigure 26. PCMCIA WAIT Signal Detection TimingMOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 33

Layout Practices

Table 9 shows the PCMCIA port timing for the MPC850.

Table 9. PCMCIA Port Timing

50 MHzNumP57P58P59P60166 MHzMin—26.005.001.00Max19.00———80 MHzUnitMin—22.005.001.00Max19.00———nsnsnsnsCharacteristicMinCLKOUT to OPx validHRESET negated to OPx drive 1IP_Xx valid to CLKOUT rising edgeCLKOUT rising edge to IP_Xx invalid—18.005.001.00Max19.00———OP2 and OP3 only.Figure 27 provides the PCMCIA output port timing for the MPC850.

CLKOUT

P57OutputSignals

HRESET

P58OP2, OP3

Figure 27. PCMCIA Output Port Timing

Figure 28 provides the PCMCIA output port timing for the MPC850.

CLKOUT

P59P60InputSignals

Figure 28. PCMCIA Input Port Timing

34MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Table 10 shows the debug port timing for the MPC850.

Table 10. Debug Port Timing

50 MHz

NumD61D62D63DD65D66D67

Characteristic

Min

DSCK cycle timeDSCK clock pulse widthDSCK rise and fall timesDSDI input data setup timeDSDI data hold time

DSCK low to DSDO data validDSCK low to DSDO invalid

60.0025.000.008.005.000.000.00

Max——3.00——15.002.00

Min91.0038.000.008.005.000.000.00

Max——3.00——15.002.00

Min75.0031.000.008.005.000.000.00

Max——3.00——15.002.00

nsnsnsnsnsnsns

66 MHz

80 MHz

Unit

Figure 29 provides the input timing for the debug port clock.

DSCK

D61D62D62D63D63Figure 29. Debug Port Clock Input Timing

Figure 30 provides the timing for the debug port.

DSCK

DD65DSDI

D66D67DSDO

Figure 30. Debug Port Timings

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 35

Layout Practices

Table 11 shows the reset timing for the MPC850.

Table 11. Reset Timing

50 MHz

NumR69R70R71R72R73R74R75R76R77R78

Configuration data to HRESET rising edge set up time

Characteristic

Min

CLKOUT to HRESET high impedanceCLKOUT to SRESET high impedanceRSTCONF pulse width——340.00—350.00

Max20.0020.00——————25.0025.0025.00

Min——515.00—505.00350.000.000.00———

Max20.0020.00——————25.0025.0025.00

Min——425.00—425.00350.000.000.00———

Max20.0020.00——————25.0025.0025.00

——17.000—15.000——————

nsnsnsnsnsnsnsnsnsns

66MHz

80 MHz

FFACTORUnit

Configuration data to RSTCONF rising 350.00edge set up time

Configuration data hold time after RSTCONF negationConfiguration data hold time after HRESET negationHRESET and RSTCONF asserted to data out drive

RSTCONF negated to data out high impedance.

CLKOUT of last rising edge before chip tristates HRESET to data out high impedance.DSDI, DSCK set upDSDI, DSCK hold time

SRESET negated to CLKOUT rising edge for DSDI and DSCK sample

0.000.00———

R79R80R81R82

60.000.00160.00

———

90.000.00242.00

———

75.000.00200.00

———

3.000—8.000

nsnsns

Figure 31 shows the reset timing for the data bus configuration.

HRESETR71R76RSTCONFR73R74D[0:31] (IN)R75Figure 31. Reset Timing—Configuration from Data Bus

36MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Layout Practices

Figure 32 provides the reset timing for the data bus weak drive during configuration.

CLKOUT

R69HRESET

R79RSTCONF

R77D[0:31] (OUT)

(Weak)

R78Figure 32. Reset Timing—Data Bus Weak Drive during Configuration

Figure 33 provides the reset timing for the debug port configuration.

CLKOUT

R70R82SRESET

R80R81DSCK, DSDI

R80R81Figure 33. Reset Timing—Debug Port Configuration

Part VII IEEE 1149.1 Electrical Specifications

Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37.

Table 12. JTAG Timing

50 MHz

NumJ82J83J84J85

TCK cycle time

TCK clock pulse width measured at 1.5 VTCK rise and fall timesTMS, TDI data setup time

Characteristic

Min100.0040.000.005.00

Max——10.00—

Min100.0040.000.005.00

Max——10.00—

Min100.0040.000.005.00

Max——10.00—

nsnsnsns

66MHz

80 MHz

Unit

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 37

Layout Practices

Table 12. JTAG Timing (continued)

50 MHz

NumJ86J87J88JJ90J91J92J93J94J95J96

Characteristic

Min

TMS, TDI data hold timeTCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert timeTRST setup time to TCK lowTCK falling edge to output valid

TCK falling edge to output valid out of high impedance

TCK falling edge to output high impedanceBoundary scan input valid to TCK rising edgeTCK rising edge to boundary scan input invalid

25.00—0.00—100.0040.00———50.0050.00

Max—27.00—20.00——50.0050.0050.00——

Min25.00—0.00—100.0040.00———50.0050.00

Max—27.00—20.00——50.0050.0050.00——

Min25.00—0.00—100.0040.00———50.0050.00

Max—27.00—20.00——50.0050.0050.00——

nsnsnsnsnsnsnsnsnsnsns

66MHz

80 MHz

Unit

TCK

J82J82J84J83J83J84Figure 34. JTAG Test Clock Input Timing

TCK

J85J86TMS, TDI

J87J88TDO

JFigure 35. JTAG Test Access Port Timing Diagram

38MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

PIO AC Electrical Specifications

TCK

J91J90TRST

Figure 36. JTAG TRST Timing DiagramTCK

J92OutputSignals

J93OutputSignals

J95InputSignals

J96J94Figure 37. Boundary Scan (JTAG) Timing Diagram

Part VIII CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module(CPM) of the MPC850.

8.1PIO AC Electrical Specifications

Table 13. Parallel I/O Timing

All Frequencies

Table 13 provides the parallel I/O timings for the MPC850 as shown in Figure 38.

Num293031

Characteristic

Min

Data-in setup time to clock highData-in hold time from clock high

Clock low to data-out valid (CPU writes data, control, or direction)

157.5—

Max——25

Unitnsnsns

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 39

IDMA Controller AC Electrical Specifications

CLKOUT

2930DATA-IN

31DATA-OUT

Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram

8.2IDMA Controller AC Electrical Specifications

Table 14. IDMA Controller Timing

All Frequencies

Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42.

Num40414243444546

DREQ setup time to clock highCharacteristic

Min7.003.00————7.00

Max——12.0012.0020.0015.00—

Unitnsnsnsnsnsnsns

DREQ hold time from clock highSDACK assertion delay from clock highSDACK negation delay from clock lowSDACK negation delay from TA lowSDACK negation delay from clock highTA assertion to falling edge of the clock setup time (applies to external TA)CLKOUT(Output)

40DREQ(Input)

41Figure 39. IDMA External Requests Timing Diagram

40MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

IDMA Controller AC Electrical Specifications

CLKOUT(Output)TS(Output)R/W(Output)42DATA46TA(Output)43SDACKFigure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge of the ClockCLKOUT(Output)TS(Output)R/W(Output)42DATA44TA(Output)SDACKFigure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge of the Clock

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 41

Baud Rate Generator AC Electrical Specifications

CLKOUT(Output)

TS(Output)

R/W(Output)

42DATA

45TA(Output)

SDACK

Figure 42. SDACK Timing Diagram—Peripheral Read8.3Baud Rate Generator AC Electrical SpecificationsTable 15. Baud Rate Generator TimingAll FrequenciesNum505152CharacteristicMinBRGO rise and fall time BRGO duty cycleBRGO cycle—40.0040.00Max10.0060.00—ns%nsUnitTable 15 provides the baud rate generator timings as shown in Figure 43.50BRGOn

51525051Figure 43. Baud Rate Generator Timing Diagram

42MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Timer AC Electrical Specifications

8.4

Timer AC Electrical Specifications

Table 16. Timer Timing

All FrequenciesNum61626365CharacteristicMinTIN/TGATE rise and fall timeTIN/TGATE low timeTIN/TGATE high timetimeTIN/TGATE cycle CLKO high to TOUT valid10.001.002.003.003.00Max————25.00nsclkclkclknsUnitTable 16 provides the baud rate generator timings as shown in Figure 44.

CLKOUT61TIN/TGATE(Input)6165TOUT(Output)6362Figure 44. CPM General-Purpose Timers Timing Diagram8.5Serial Interface AC Electrical SpecificationsTable 17. SI Timing All FrequenciesNum707171a7273Characteristic MinL1RCLK, L1TCLK frequency (DSC = 0) 1, 2 —L1RCLK, L1TCLK width low (DSC = 0) 2L1RCLK, L1TCLK width high (DSC = 0) 3L1TXD, L1STn, L1RQ, L1xCLKO rise/fall timeL1RSYNC, L1TSYNC valid to L1xCLK edge Edge (SYNC setup time)P + 10P + 10—20.00MaxSYNCCLK/2.5——15.00—MHznsnsnsnsUnitTable 17 provides the serial interface timings as shown in Figure 45 to Figure 49.MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 43

Serial Interface AC Electrical Specifications

Table 17. SI Timing (continued)

All FrequenciesNum747576777878A798080A81828383A848586878812

Characteristic Min L1xCLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time)L1RSYNC, L1TSYNC rise/fall timeL1RXD valid to L1xCLK edge (L1RXD setup time)L1xCLK edge to L1RXD invalid (L1RXD hold time)L1xCLK edge to L1STn valid 4L1SYNC valid to L1STn validL1xCLK edge to L1STn invalidL1xCLK edge to L1TXD validL1TSYNC valid to L1TXD valid 4L1xCLK edge to L1TXD high impedanceL1RCLK, L1TCLK frequency (DSC =1)L1RCLK, L1TCLK width low (DSC =1)L1RCLK, L1TCLK width high (DSC = 1)3L1CLK edge to L1CLKO valid (DSC = 1)L1RQ valid before falling edge of L1TSYNC4L1GR setup time2L1GR hold timeL1xCLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0)35.00—17.0013.0010.0010.0010.0010.0010.000.00—P + 10P + 10—1.0042.0042.00—Max—15.00——45.0045.0045.0055.0055.0042.0016.00 or SYNCCLK/2——30.00———0.00UnitnsnsnsnsnsnsnsnsnsnsMHznsnsnsL1TCLKnsnsnsThe ratio SyncCLK/L1RCLK must be greater than 2.5/1.These specs are valid for IDL mode only.

3Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.

4These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.

44MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Serial Interface AC Electrical Specifications

L1RCLK(FE=0, CE=0)

(Input)

7172L1RCLK(FE=1, CE=1)

(Input)

RFSD=175L1RSYNC(Input)

7374L1RxD(Input)

7678L1STn(Output)

79BIT0777071aFigure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 45

Serial Interface AC Electrical Specifications

L1RCLK(FE=1, CE=1)

(Input)

7282L1RCLK(FE=0, CE=0)

(Input)

RFSD=175L1RSYNC

(Input)

7374L1RXD(Input)

7678L1ST(4-1)(Output)

79BIT07783a84L1CLKO(Output)

Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1)

46MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Serial Interface AC Electrical Specifications

L1TCLK(FE=0, CE=0)

(Input)

7172L1TCLK(FE=1, CE=1)

(Input)

7073TFSD=075L1TSYNC(Input)

7480aL1TxD(Output)

8078L1STn(Output)

79BIT081Figure 47. SI Transmit Timing Diagram

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 47

Serial Interface AC Electrical Specifications

L1RCLK(FE=0, CE=0)

(Input)

7282L1RCLK(FE=1, CE=1)

(Input)

TFSD=075L1RSYNC

(Input)

7374L1TXD(Output)

BIT08078aL1ST(4-1)(Output)

7884L1CLKO(Output)

798183aFigure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1)

48MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

MOTOROLA

3714567101112131415161718192071B15B14B137281B12B11B10D1AB27B26B25B24B23B22B21B20D2MB12B11B10D1AB27B26B25B24B23B22B21B20D2M7887L1RCLK(Input)1273L1RSYNC(Input)8074L1TXD(Output)B17B1677L1RXD(Input)B17B16B15B14B13Figure 49. IDL Timing

76L1ST(4-1)(Output)MPC850 (Rev. A/B/C) Hardware Specifications

85L1RQ(Output)86L1GR(Input)Serial Interface AC Electrical Specifications

49

SCC in NMSI Mode Electrical Specifications

8.6

SCC in NMSI Mode Electrical Specifications

Table 18. NMSI External Clock Timing

All FrequenciesTable 18 provides the NMSI external clock timing.

Num100101 102 103 104105106107CharacteristicMinRCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table)RCLKx and TCLKx width lowRCLKx and TCLKx rise/fall timeTXDx active delay (from TCLKx falling edge)RTSx active/inactive delay (from TCLKx falling edge)CTSx setup time to TCLKx rising edgeRXDx setup time to RCLKx rising edgeRXDx hold time from RCLKx rising edge 21/SYNCCLK1/SYNCCLK +5—0.000.005.005.005.005.00Max——nsns Unit15.00ns50.00ns50.00ns————nsnsnsns108 CDx setup time to RCLKx rising edge12The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.Also applies to CD and CTS hold time when they are used as an external sync signal.Table 19 provides the NMSI internal clock timing. Table 19. NMSI Internal Clock Timing All FrequenciesNum100102 103 104105106107108Characteristic MinRCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table)RCLKx and TCLKx rise/fall timeTXDx active delay (from TCLKx falling edge)RTSx active/inactive delay (from TCLKx falling edge)CTSx setup time to TCLKx rising edgeRXDx setup time to RCLKx rising edgeRXDx hold time from RCLKx rising edge 2CDx setup time to RCLKx rising edge0.00—0.000.0040.0040.000.0040.00 MaxSYNCCLK/3—30.0030.00————MHznsnsnsnsnsnsns Unit12

The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.Also applies to CD and CTS hold time when they are used as an external sync signals.50MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

SCC in NMSI Mode Electrical Specifications

Figure 50 through Figure 52 show the NMSI timings.

RCLKx

102106RXDx(Input)

107108CDx (Input)

102101100107CDx

(SYNC Input)

Figure 50. SCC NMSI Receive Timing Diagram

TCLKx

102102101100TXDx(Output)

103105RTSx (Output)

104104CTSx (Input)

107CTSx

(SYNC Input)

Figure 51. SCC NMSI Transmit Timing Diagram

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 51

Ethernet Electrical Specifications

TCLKx

102102101100TXDx(Output)

103RTSx (Output)

104105CTSx(Echo Input)

107104Figure 52. HDLC Bus Timing Diagram

8.7Ethernet Electrical Specifications

Table 20. Ethernet Timing

All Frequencies

Num120121122123124125126127128129130131132

CLSN width high

RCLKx rise/fall time (x = 2, 3 for all specs in this table)RCLKx width lowRCLKx clock period 1RXDx setup timeRXDx hold time

RENA active delay (from RCLKx rising edge of the last data bit)RENA width lowTCLKx rise/fall time TCLKx width lowTCLKx clock period1TXDx active delay (from TCLKx rising edge)TXDx inactive delay (from TCLKx rising edge)

Characteristic

Min40.00—40.0080.0020.005.0010.00100.00—40.0099.0010.0010.00

Max—15.00—120.00————15.00—101.0050.0050.00

nsnsnsnsnsnsnsnsnsnsnsnsnsUnit

Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55.

52MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Ethernet Electrical Specifications

Table 20. Ethernet Timing (continued)

All FrequenciesNum13313413813912

CharacteristicMinTENA active delay (from TCLKx rising edge)TENA inactive delay (from TCLKx rising edge)CLKOUT low to SDACK asserted 2CLKOUT low to SDACK negated 210.0010.00——Max50.0050.0020.0020.00UnitnsnsnsnsThe ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1.SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory.CLSN(CTSx)(Input)

120Figure 53. Ethernet Collision Timing Diagram

RCLKx

121121124RXDx(Input)

125126127RENA(CDx)

(Input)

122123Last BitFigure 54. Ethernet Receive Timing Diagram

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 53

SMC Transparent AC Electrical Specifications

TCLKx128131TxDx(Output)132133TENA(RTSx) (Input)134128130129RENA(CDx) (Input)(NOTE 2)NOTES:

1.Transmit clock invert (TCI) bit in GSMR is set.

2.If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then theCSL bit is set in the buffer descriptor at the end of the frame transmission.

Figure 55. Ethernet Transmit Timing Diagram

8.8SMC Transparent AC Electrical Specifications

Table 21. Serial Management Controller Timing

All FrequenciesNum150151151a1521531541551Figure 21 provides the SMC transparent timings as shown in Figure 56.

CharacteristicMinSMCLKx clock period 1SMCLKx width lowSMCLKx width highSMCLKx rise/fall time SMTXDx active delay (from SMCLKx falling edge)SMRXDx/SMSYNx setup timeSMRXDx/SMSYNx hold time100.0050.0050.00—10.0020.005.00Max———15.0050.00——UnitnsnsnsnsnsnsnsThe ratio SyncCLK/SMCLKx must be greater or equal to 2/1.54MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

SPI Master AC Electrical Specifications

SMCLKx152152151151a150SMTXDx(Output)154155SMSYNx154155SMRXDx (Input)NOTE:

1.This delay is equal to an integer number of character-length clocks.

NOTE 153Figure 56. SMC Transparent Timing Diagram

8.9SPI Master AC Electrical Specifications

Table 22. SPI Master Timing

All Frequencies

Num1601611621631165166167

Characteristic

Min

MASTER cycle time

MASTER clock (SCK) high or low timeMASTER data setup time (inputs)Master data hold time (inputs)Master data valid (after SCK edge)Master data hold time (outputs)Rise time outputFall time output

4250.000.00—0.00——

Max1024512——20.00—15.0015.00

tcyctcycnsnsnsnsnsnsUnit

Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58.

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 55

SPI Master AC Electrical Specifications

SPICLK(CI=0)(Output)

161161SPICLK(CI=1)(Output)

163162SPIMISO(Input)

msb166Data165167SPIMOSI(Output)

msbDatalsblsb1166msbmsb167167160166Figure 57. SPI Master (CP = 0) Timing DiagramSPICLK(CI=0)(Output)

161161SPICLK(CI=1)(Output)

163162SPIMISO(Input)

msb166Data165167SPIMOSI(Output)

msbDatalsblsb1166msbmsb167167160166Figure 58. SPI Master (CP = 1) Timing Diagram

56MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

SPI Slave AC Electrical Specifications

8.10SPI Slave AC Electrical Specifications

Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60.

Table 23. SPI Slave Timing

All Frequencies

Num170171172173174175176177178179180181182

Slave cycle timeSlave enable lead timeSlave enable lag time

Slave clock (SPICLK) high or low time

Slave sequential transfer delay (does not require deselect)Slave data setup time (inputs)Slave data hold time (inputs)Slave access time

Slave SPI MISO disable timeSlave data valid (after SPICLK edge)Slave data hold time (outputs)Rise time (input)Fall time (input)

Characteristic

Min215.0015.001120.0020.00———0.00——

Max———————50.0050.0050.00—15.0015.00

tcycnsnstcyctcycnsnsnsnsnsnsnsnsUnit

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 57

SPI Slave AC Electrical Specifications

SPISEL(Input)172174SPICLK(CI=0)(Input)173173SPICLK(CI=1)(Input)177180SPIMISO(Output)msb175176SPIMOSI(Input)msbDataData179181182lsbmsblsb181182178Undefmsb182170181171Figure 59. SPI Slave (CP = 0) Timing Diagram

58MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

I2C AC Electrical Specifications

SPISEL(Input)172171SPICLK(CI=0)(Input)173173SPICLK(CI=1)(Input)177180SPIMISO(Output)Undef175176SPIMOSI(Input)msbmsb179181182DatalsbmsbDatalsb182178msb182181181170174Figure 60. SPI Slave (CP = 1) Timing Diagram

8.11I2C AC Electrical Specifications

Table 24 provides the I2C (SCL < 100 KHz) timings.

Table 24. I2C Timing (SCL < 100 KHZ)

All Frequencies

Num200200202203204205206207

Characteristic

Min

SCL clock frequency (slave)SCL clock frequency (master) 1Bus free time between transmissions Low period of SCLHigh period of SCLStart condition setup timeStart condition hold timeData hold time

0.001.504.704.704.004.704.000.00

Max100.00100.00——————

KHzKHzµsµsµsµsµsµsUnit

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 59

I2C AC Electrical Specifications

Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED)

All FrequenciesNum2082092102111CharacteristicMinData setup timeSDL/SCL rise time SDL/SCL fall time Stop condition setup time250.00——4.70Max—1.00300.00—UnitnsµsnsµsSCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.Table 25 provides the I2C (SCL > 100 KHz) timings.Table 25. I2C Timing (SCL > 100 KHZ) All FrequenciesNum2002002022032042052062072082092102111CharacteristicSCL clock frequency (slave)SCL clock frequency (master) 1Bus free time between transmissions Low period of SCLHigh period of SCLStart condition setup timeStart condition hold timeData hold timeData setup timeSDL/SCL rise time SDL/SCL fall time Stop condition setup timeExpressionMinfSCLfSCL0BRGCLK/165121/(2.2 * fSCL)1/(2.2 * fSCL)1/(2.2 * fSCL)1/(2.2 * fSCL)1/(2.2 * fSCL)01/(40 * fSCL)——1/2(2.2 * fSCL)MaxBRGCLK/48BRGCLK/48———————1/(10 * fSCL)1/(33 * fSCL)—UnitHzHzssssssssssSCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.

60MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

I2C AC Electrical Specifications

Figure 61 shows the I2C bus timing.

SDA

202205SCL

206209210211203207204208Figure 61. I2C Bus Timing Diagram

Part IX Mechanical Data and Ordering Information

Table 26 provides information on the MPC850 derivative devices.

Table 26. MPC850 Derivatives

DeviceMPC850MPC850DEMPC850SAR12

Ethernet SupportN/AYes YesNumber of SCCs 1OneTwoTwo32-Channel HDLC SupportN/AN/AN/A-Channel HDLC Support 2N/AN/AYesSerial Communication Controller (SCC)50 MHz version supports time slots on a time division multiplexed line using one SCC

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 61

Pin Assignments and Mechanical Dimensions of the PBGA

Table 27 identifies the packages and operating frequencies available for the MPC850.

Table 27. MPC850 Package/Frequency/Availability

Package Type

256-Lead Plastic Ball Grid Array(ZT suffix)

Frequency (MHz)

50

Temperature (Tj)0°C to 95°C

Order NumberXPC850ZT50BXPC850DEZT50BXPC850SRZT50BXPC850ZT66BXPC850DEZT66BXPC850SRZT66BXPC850ZT80BXPC850DEZT80BXPC850SRZT80BXPC850CZT50BXPC850DECZT50BXPC850SRCZT50BXPC850CZT66BXPC850DECZT66BXPC850SRCZT66BXPC850CZT80BXPC850DECZT80BXPC850SRCZT80B

660°C to 95°C

800°C to 95°C

256-Lead Plastic Ball Grid Array(CZT suffix)

50-40°C to 95°C

66

80

9.1

Pin Assignments and Mechanical Dimensions of the PBGA

The original pin numbering of the MPC850 conformed to a Motorola proprietary pin numbering schemethat has since been replaced by the JEDEC pin numbering standard for this package type. To supportcustomers that are currently using the non-JEDEC pin numbering scheme, two sets of pinouts, JEDEC andnon-JEDEC, are presented in this document.

62MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Pin Assignments and Mechanical Dimensions of the PBGA

Figure 62 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface.

T

PC14PB28PB27PC12TCKPB24PB23PA8PA7VDDLPA5PC7PC4PD14PD10PD8R

PC15PA14PA13PA12TMSTDIPC11PB22PC9PB19PA4PB16PD15PD12PD7PD6P

PA15PB30PB29PC13PB26TRSTN/CPC10PA6PB18PC5PD13PD9PD4PD5N/CN

A8A7PB31N/CTDOPB25PA9N/CPC8PB17PC6PD11PD3IRQ7IRQ1IRQ0M

A11A9A12A6D12D13D8D0L

A15A14A13A10D23D27D4D1K

A27A19A16A17D17D10D9D11J

VDDLA20A21N/CGNDD15D14D2D3H

A29A23A25A24D22D18D16D5G

A28A30A22A18D25D20D19VDDLF

A31TSIZ0A26WE3VDDHD28D24D21D6E

WE1TSIZ1N/CGPLA0D26D31D29D7D

WE0WE2GPLA3CS5CS0GPLA4TSIRQ2IPB7IPB2MODCK1TEXPDP1DP2D30CLKOUTC

GPLA1GPLA2CS6WRGPLA5TEABGIPB5IPB1IPB6N/CRSTCONFWAITBDP0DP3N/CB

CS4CS7CS2GPLB4BIBRBURSTIPB4ALEBIRQ4MODCK2HRESETSRESETPORESETXFCVDDSYNA

N/C16

CS315

CS114

BDIP13

TA12

BB11

IRQ610

IPB39

IPB08

VDDLEXTCLKEXTAL7

6

5

VSSSYNXTALKAPWRVSSSYN14

3

2

1

Figure 62. Pin Assignments for the PBGA (Top View)—non-JEDEC Standard

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 63

Pin Assignments and Mechanical Dimensions of the PBGA

Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface.

U

PC14PB28PB27PC12TCKPB24PB23PA8PA7VDDLPA5PC7PC4PD14PD10PD8T

PC15PA14PA13PA12TMSTDIPC11PB22PC9PB19PA4PB16PD15PD12PD7PD6R

PA15PB30PB29PC13PB26TRSTN/CPC10PA6PB18PC5PD13PD9PD4PD5N/CP

A8A7PB31N/CTDOPB25PA9N/CPC8PB17PC6PD11PD3IRQ7IRQ1IRQ0N

A11A9A12A6D12D13D8D0M

A15A14A13A10D23D27D4D1L

A27A19A16A17D17D10D9D11K

VDDLA20A21N/CGNDD15D14D2D3J

A29A23A25A24D22D18D16D5H

A28A30A22A18D25D20D19VDDLG

A31TSIZ0A26WE3VDDHD28D24D21D6F

WE1TSIZ1N/CGPLA0D26D31D29D7E

WE0WE2GPLA3CS5CS0GPLA4TSIRQ2IPB7IPB2MODCK1TEXPDP1DP2D30CLKOUTD

GPLA1GPLA2CS6WRGPLA5TEABGIPB5IPB1IPB6N/CRSTCONFWAITBDP0DP3N/CC

CS4CS7CS2GPLB4BIBRBURSTIPB4ALEBIRQ4MODCK2HRESETSRESETPORESETXFCVDDSYNB

N/C17

CS316

CS115

BDIP14

TA13

BB12

IRQ611

IPB310

IPB09

VDDLEXTCLKEXTAL8

7

6

VSSSYNXTALKAPWRVSSSYN15

4

3

2

Figure 63. Pin Assignments for the PBGA (Top View)—JEDEC Standard

For more information on the printed circuit board layout of the PBGA package, including thermal via design

and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note availablefrom your local Motorola sales office.

MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Pin Assignments and Mechanical Dimensions of the PBGA

Figure shows the non-JEDEC package dimensions of the PBGA.

ADD20.35CNOTES:

1.DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2.DIMENSIONS IN MILLIMETERS.

3.DIMENSION b IS MEASURED AT THE MAXIMUM

SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C.

4.PRIMARY DATUM C AND THE SEATING PLANE ARE

DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

MILLIMETERSMINMAX1.912.350.500.701.121.220.290.430.600.9023.00 BSC19.05 REF19.0020.0023.00 BSC19.05 REF19.0020.001.27 BSC

256X0.20CEE24X0.20A2A3A1ACSEATINGPLANETOP VIEWB(D1)15XDIMAA1A2A3bDD1D2EE1E2e

eTRPNMLKJHGFEDCBASIDE VIEW15Xe(E1)4Xe/2123456710111213141516256Xb0.300.15

MMBOTTOM VIEW

CABC

Figure . Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard

MOTOROLAMPC850 (Rev. A/B/C) Hardware Specifications 65

Pin Assignments and Mechanical Dimensions of the PBGA

Figure 65 shows the JEDEC package dimensions of the PBGA.

ADD20.35CNOTES:

1.DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2.DIMENSIONS IN MILLIMETERS.

3.DIMENSION b IS MEASURED AT THE MAXIMUM

SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C.

4.PRIMARY DATUM C AND THE SEATING PLANE ARE

DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

MILLIMETERSMINMAX1.912.350.500.701.121.220.290.430.600.9023.00 BSC19.05 REF19.0020.0023.00 BSC19.05 REF19.0020.001.27 BSC

256X0.20CEE24X0.20A2A3A1ACSEATINGPLANETOP VIEWB(D1)15XDIMAA1A2A3bDD1D2EE1E2e

eUTRPNMLKJHGFEDCBSIDE VIEW15Xe(E1)4Xe/22345671011121314151617256Xb0.300.15

MMBOTTOM VIEW

CABC

CASE 1130-01ISSUE B

Figure 65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard

66MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

Pin Assignments and Mechanical Dimensions of the PBGA

Part X Document Revision History

Table 28 lists significant changes between revisions of this document.

Table 28. Document Revision History

Revision0.1

Date11/2001

Change

Removed reference to 5 Volt tolerance capability on peripheral interface pins. Replaced SI and IDL timing diagrams with better images. Put into new template, added this revision table.

Put in the new power numbers and added Rev. C

0.204/2002

67MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA

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