VHDL整理,华工VHDL,数字系统设计,习题答案参考,试卷资料,电信学院大三

1.CPLD :Complex programmable logic devices (based on 乘积项) 2.FPGA：Field Programmable Gate Array（based on LUT）

3.PROM:与阵列固定，或阵列可编程(巧记，有个O，联想到or,所以是或)

4.PLA：与或阵列均可编程（巧记，pla,两个音，所以与或都有） 5.PAL，GAL：与阵列可编程，或阵列不可编程（巧记，一个音，是与）

6.Digital system design is based on programmable logic devices (PLD).It is top-down design,suing EDA. 7.VHDL

a) Strong capability of system description b) Independence of device and hardware technique c) IEEE standard

d) Flexible design method(behav,struc,dataflow) e) Readable program

f) As an HDL,executed concurrently structurc of VHDL:（目测填空题）

LIBRARY, Package, Entity, Architecture, Configuration, Block, Sub-program, 8.Default Library（默认库）:STD,work

9.MOD（取模），REM（取余），ABS（取绝对值），SLA（算数左移）

SRA（算数右移），SRL（逻辑右移），SLL（逻辑左移），ROR，ROL 10.Different package------>different physic circuit; 11.Entity-------outward appearence

12.Architecture--------describe the function or structure of the circuit 13.Input-------can not be assign the value 14.Output------can not be the source of assignment 15.Inout-------bi-directional port

16.Buffer-------serve as an output,its value can be reloaded 17.Architecture description a) Behavior description b) Data flow description c) Structure description 18.字符用’ ’,字符串用” ”

19.实体名不能用数字开头，实体名要与文件名一致 20.VHDL data type

Integer, real, natural, bit, bit_vector, std_logic, std_logic_vector, character, string, boolean, time, severity level 21.’Z’ high impedance 22.‘X’ forcing unknown

23.自定义数组TYPE word8 IS ARRY (1 TO 8) OF BIT; 24.VHDL data object: constant, variable, signal 25.signal:

1.has corresponding hardware, 2.global,for multiple process 3.assignment has delay, 4.can carry history information 26.variable:

1.has no corresponding hardware 2.local,valid in its process only 3.assignment takes effect immediately 4.has current value only

27.sequential statements should be packaged in process

28.（重点）when ..else是并行语句，不用process包起来，但是它 是具有顺序性的，考试时一般考它与if语句的改写，注意，if语句 是顺序语句，得用process包起来 （重点）with..select是并行语句，也不用process包起来，它没29. 有顺序性，且条件必须涵盖完全，也就是说若没有全例举出来最后 要有..when others，考试一般考改写case语句 注意：if语句和case也可以相互改写，要根据题目改写，书写顺序要小心，特别是优先级编码器

30.PROCESS，注意，它是

，只是它里面是

一般考改写wait语句,有wait on+信号表和wait until+条件两种，注意，PROCESS还是要写的，只是不用加（）而已，别以为有wait就不能有PROCESS 31.process的特点（一般是选择题）

32.sequential statement(顺序语句)有if statement,case statement,loop statement,next statement,exit statement,wait statement,return,null 33.两种电路的区别

34.选择题考encoder和decoder要看清楚

inputs是inputs是

的是decoder

的是encoder

计算机存储信息和传输信息都是binary codes，所以encoder是为了

方便

35.要会画decoder和encoder的

Half adder里面，Sum用or, carry用and 36.37.

Full adder有38.这个

要会画

和

两种

39.sequential logic circuits

40.同步能

（Moore型就是同步的,同步可以消除亚稳态）简单可靠，但是耗

41.异步

(Mealy型就是异步的，容易出现亚稳态)

42.D锁存器（重）

名词解释

分别为：锁存器，触发器，寄存器，计数器，乘法器

43.触发器

44.注意

clk只能是std_logic,不能是bit

45.带复位和Qbar的D触发器要小心(考改错题)

考点1：加一个信号作为中间值 考点2：复位是不用考虑时钟沿的， 所以写在时钟沿检测之前 考点3：Q和Qbar赋值放到PROCESS外面 其实凡是带bar的都是这样设一个signal作为中间值的，如果不这样做，直接在PROCESS用D给Q和用not D给Qbar赋值，综合时会综合成两个触发器。注意用signal才能放到PROCESS外，用variable的话就要放PORCESS里面，建议用signal

46.register寄存器，（D_F.F其实就是一个one bit的register） 多位的register可以用多个D_F.F组成

47.48.

这句赋值的意思是Q赋全0 移位寄存器

分别为串进串出，串进并出，并进串出，（S是串，P是并）

串进并出的例子

串进，第n-1位被踢掉，所以最高位变成n-2 位 并出 49.State machine状态机

finite number of states有限种状态 FSM就是有限状态的状态机 其实它是用来描述sequential logic的

Next state logic（一般用ns） Combinational logic sequential logic Output logic(一般用op) Memory units(一般用seq)

分别对Next state logic，Output logic，Memory units写进程，这就是课本分三进程的分法，其中Next state logic，Output logic可以放在一个进程里，这样就是双进程的状态机了（考试要求掌握双进程状态机） 50.Race and Hazard（竞争与冒险）

Signals through different paths arrive at the same node with time difference because of different propagation delays, which may causes transient error in output

说白了，就是没有同步，超级赛亚人合体没同步就会变成“变体” 所以避免竞争冒险可以用同步时序逻辑电路

Race and Hazard can be avoided by synchronous（同步） sequential logic

51.ASM图的特点

1.used for synchronous sequential system（用于同步时序逻辑电路） 2.ASM can represent the exact timing relations between state transitions （可以表现不同状态之间的时序关系）

3.It resembles software flow chart, but it has corresponding hardware structure.（它有对应的硬件） 52，ＡＳＭ图（重点） onditional output box条件框 Decision box判断框 State box状态框

R<-0 注意 表示R在状态末赋0值,然后保持，直到下次赋值

’1 Ｚ = ’ 和 Ｚ 一样，都是表示在这个状态时Z赋值1，

过了这个状态就变为0

53.要会根据ASM图画波形图（注意条件框与它所属的状态框是同一个状态的，画波形图的时候要小心）

54.要会根据电路图画ASM图（重重重重点，大题）

方法，先根据电路图写驱动方程和输出方程，然后根据方程画状态转换表，再根据状态转换表画ASM图

0X0&0Z20&0Z100

Q1n+1 QD

Q

Q2n+1QD

Q

CP

00SETCLR&

55.Moore machine

The output depends on the present state only，the output is solely a function of the present state.

The output of Moore machine is independent of current input The output part and input part are separated

56.Mealy Machine（比Moore结构复杂，complicated）

The output depends on both the present state and the input，the output is a function of the present state and of input

一定要 搞 懂 If the input changes, the output can change during the current state.

57.One-process state machine单进程状态机

State transition, next state logic, and output logic are included in a single process.

58.two-process state machine双进程状态机（大题）

TIMEDRSTART_TIME0CAR GMAJOR=GRNMINOR=RED重点，不解释 1 MAJOR=REDMINOR=GRNLIBRARY IEEE ;

USE IEEE.STD_LOGIC_11.ALL ; ENTITY traffic IS

PORT( clock , timed , car : IN std_logic ; start_timer, major_green, minor_green : OUT std_logic ); END ENTITY traffic ;

ARCHITECTURE asm2 OF traffic IS TYPE state_type IS (G, R); --利用枚举类型定义状态 SIGNAL pr_state, nx_state : state_type;

--将状态机的现态、次态定义为全局信号，便于在进程间传递信息 BEGIN

seq: PROCESS (clock) BEGIN IF(rising_edge(clock)) THEN pr_state <= nx_state;--次态是寄存器的输入 END IF; --条件涵盖不完整的if语句产生状态寄存器 END PROCESS seq; --产生状态寄存器的进程 com: PROCESS (pr_state, car, timed) BEGIN start_timer <= ‘0’; CASE pr_state IS WHEN G => major_green <= ‘1’; minor_green <= ‘0’; IF (car = ‘1’) THEN start_timer <= ‘1’; nx_state <= R; ELSE nx_state <= G; END IF; WHEN R => major_green <= ‘0’; minor_green <= ‘1’; IF (timed= ‘1’) THEN nx_state <= G; ELSE nx_state <= R; END IF; END CASE; END PROCESS com; --产生次态和输出逻辑的进程 END asm2;

59.three-process state machine三进程状态机

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_11.ALL ; ENTITY traffic IS

PORT( clock , timed , car : IN std_ulogic ; start_timer, major_green, minor_green : OUT std_ulogic ); END ENTITY traffic ;

ARCHITECTURE asm2 OF traffic IS TYPE state_type IS (G, R); --利用枚举类型定义状态 SIGNAL pr_state, nx_state : state_type;

--将状态机的现态、次态定义为全局信号，便于在进程间传递信息 BEGIN

seq: PROCESS (clock) BEGIN IF(rising_edge(clock)) THEN pr_state <= nx_state;--次态是寄存器的输入 END IF; --条件涵盖不完整的if语句产生状态寄存器 END PROCESS seq; --产生状态寄存器的进程

ns: PROCESS (car, timed, pr_state) --process of next state logic BEGIN CASE pr_state IS WHEN G => IF (car = ‘1’) THEN nx_state <= R; ELSE nx_state <= G; WHEN R => IF (timed = ‘1’) THEN nx_state <= G; ELSE nx_state <= R; END IF; END CASE;

END PROCESS ns;

op: PROCESS (car, pr_state) –Mealy or Moore? --process for output logic BEGIN start_timer <= ‘0’; IF (pr_state = G) THEN major_green <= ‘1’; minor_green <= ‘0’;

IF (car = ‘1’) THEN

start_timer <= ‘1’; END IF; ELSE major_green <= ‘0’; minor_green <= ‘1’; END IF;

END PROCESS op; END asm3；

60.Natural Binary coding（CPLD）适合小系统

例 “00” for state 1 “01” for state 2 “10” for state 3 “11” for state 4 61.Gray code（CPLD）适合小系统

The transition between neighbor states causes only 1-bit change 例 “00” for state 1 “01” for state 2 “11” for state 3 “10” for state 4 62.One-hot code（FPGA）适合大系统

例 ’0001’ ‘0010’ ‘0100’ ’1000’

63.testbench(重重重重点，大题)

一句话，要会写testbench（格式相当重要，背，记！） 在testbench里，clock signal，reset signal等怎么写，要会！！！

例：简述仿真测试平台的基本架构（4分）；试用VHDL语言编写测试平台文

件(Testbench)，要求testbench产生的时钟周期为100ns；复位信号0电平有效，且起始时刻为0,100ns后变为1。（12分） 被测文件的实体如下所示： ENTITY sin_gen IS PORT (

rst : IN STD_LOGIC; clk : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );

END sin_gen;

解：

library ieee;

use ieee.std_logic_11.all; entity sin_gen_tb is

注意，实体是空的 end sin_gen_tb;

architecture TB of singen_tb is component sin_gen

Component部分,把题目的 port( clk : in std_logic; rst : in std_logic; 实体端口抄一遍 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); end component;

信号声明，对应端口名，加 signal clk_t : std_logic; signal rst_t : std_logic; 个_t signal q_t : STD_LOGIC_VECTOR(7 DOWNTO 0); begin

DUT : sin_gen

DUT，注意箭 port map ( clk => clk_t, rst => rst_t, q => q_t ); 头 STIMULUS: process

begin

rst_t <= '0';

wait for 100 ns; --0 fs rst_t <= '1'; wait for 1 us; 这部分按题目要求产生信号，产生wait; 的时钟周期为100ns；复位信号end process; 0电平有效，且起始时刻为CLOCK: process 0,100ns后变为1。 begin

clk_t <= '0';

wait for 50 ns;

clk_t <= '1';

wait for 50 ns; end process; end TB;

.Design optimization（优化）

涉及race and hazard的知识

涉及flip-flop，latch等的引入问题（看课本第七章P103~P117）

avoid unwanted registers的方法

1.Combinational logic description has no edge-triggered states 2.Complete IF statement

3.Complete signal assignment in CASE statement, if a signal or variable is assigned a value in one branch, it should be assigned values in every branch, otherwise, it should be given a initial value before the execution of case statement.

65.Set up time:To ensure reliable operation, the input to a register must be stable for a minimum time before the clock edge Hold time:To ensure reliable operation, the input to a register must be stable for a minimum time after the clock edge 66.If a signal transition violates a register’s tSU（set up time） or tH (hold time)requirements, the output of the register may go into a metastable state（亚稳态）

67.In synchronous systems, the input signals must always meet the register timing requirements, so metastability does not occur.

在同步系统中。没有亚稳态

68.Synthesis（综合）

Synthesis levels:（目测填空选择题）

1.high level synthesis, 2.RTL synthesis, 3.logic synthesis, 4.layout synthesis 69.High level synthesis：（目测选择题）

translation from algorithmic(算法) behavior description to RTL description从算法级的行为描述转换到寄存器传输级描述的过程

Normally, the physic hardware structure for a high level description is not unique, the main objective of high level synthesis is to find an optimal structure with respect to the cost and constraints（约束）. 综合结果不唯一，这点喜欢考选择题，选择题喜欢说它是唯一的，喜欢考选错误的，选它

For the same VHDL description, different synthesis results may obtained depends on different synthesis tools.

70.logic synthesis：translation from RTL description to logic gate netlist（网表）

要达到higher speeds covering smaller surface areas 做到它们的balance

71.Constraints（约束）for synthesis can be described by user-defined attributes,which will be omitted in simulation

就是说仿真的时候你的那些约束条件是被忽略的

注：芯片的surface areas和系统的speeds是主要的两个约束

72.a process includes at most one clock signal

一个process里只能有一个时钟信号

73.Delay is omitted by most of existing synthesizer延时会被综合器忽略 74.Synchronous design are preferred同步设计比较受欢迎

75.For asynchronous design, synthesis results usually need to be optimized by designer.异步设计往往综合后还需人工优化 76 A).type Boolean is (FALSE , TRUE);

B).type State_type is (HALT,READY,RUN,ERROR);

C).type Std_logic is (‘U’,‘X’,‘0’, ‘1’, ‘Z’, ‘-’); D).type My_integer is Integer range 0 to 255; E).subtype Byte_int is Integer range -128 to 127; tF).ype Word is array （31 downto 0) of Bit;

G).type My_RAM is array (1023 downto 0 ) of Word; H). type RegName is (AX, BX, CX, DX); type Operation is record Mnemonic : String (1 to 10); OpCode : Bit_Vector(3 downto 0); Op1, Op2, Res : RegName; end record; 76.If statement can be synthesized into Mux or basic logic gates.

77.Case statement is synthesized into Mux.Case statement needs more logic resources

78.The synthesis of the synthesis

loop statement

is complicated in high-level

79.信号综合结果

(1) S <= A; --the resultant circuit is hardwire (2) R<= ‘1’; --R is synthesized as a constant

(3) T <= (B xor C) or (D and E) or (F xnor G);-- T is synthesized as an output of combinational logic circuit 80.

MAX7000，XC9500是属于CPLD的

基于SRAM的FPGA器件，在每次上电后必须进行一次配置 Cyclone是属于ＦＰＧＡ的

CPLD系统断电信息不丢失，保密性好 FPGA断电信息丢失，保密性差 FPGA时序资源丰富（寄存器多） Top-down:

HDL text input--->function simulation--->synthesize--->adaptation---> timing simulation---->programming and download--->test 另外固有延时和传输延时要搞懂，可能会画波形图 81.最后，重点词汇 Decoder 译码器 Encoder 编码器 Flip-flop 触发器 Latch 锁存器 Register 寄存器

Combinational logic circuit 组合逻辑电路 Structure 结构 Reflect 显示 Feedback 反馈 Multiplexer 选择器 Tri-state gate 三态门 synthesize 综合 Simulation 仿真

Corresponding 相应的 Format 码制 Conversion 转换

Sensitivity list 敏感参数表 Operation 操作 Transmission 传输

Priority encoder 优先级编码器 Implementation 实现 Arithmetic 算术 Addition 加 Subtraction 减 Multiplication 乘 Division 除

Less significant stage 低位

Account for 考虑 Modular 模块化的 Component 组成

Multi-bit adder 多位加法器 Complex 复杂的 Execute 执行

Simultaneous 同时发生的 Parallel 并行的 Feature 特征

Execute concurrently 并行执行的 Sequential 时序的，顺序的 Optimize 优化 Configuration 配置

Declaration 声明，显示 Resemble 与。。相符 Optinal 可选择的

Arab number 阿拉伯数字 Generic 属性的，类的 Assign 赋值

Bi-directional 双向的 Abstraction 抽象 Comment 注释 Identifier 标识符

High impedance 高阻态 Positive 正整数 Enumeration 枚举 Consist 由。。组成 Fixed 固定的 Computation 计算 Waveform 波形 Hardware 硬件 Triggered 触发的 K-map 卡诺图 Equation 方程式 Finite 有限的

Race and hazard 竞争与冒险 Constrains 约束 Suspend 挂起

Top-down 自顶向下 Bottom-up自底向上